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jakubcabaljakubcabal
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Merge branch 'xneckat00-axis-vector2packet' into 'devel'
Neckar axis vector2packet See merge request ndk/ndk-fpga!411
2 parents c46000e + ab1427f commit cb77964

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‎comp/axis_tools/flow/vector2packet/Modules.tcl‎

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# SPDX-License-Identifier: BSD-3-Clause
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# Copyright (C) 2026 CESNET z. s. p. o.
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# Author(s): Tomáš Neckař <xneckat00@stud.fit.vut.cz>
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# Packages
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lappend PACKAGES "$OFM_PATH/comp/base/pkg/math_pack.vhd"
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# Components
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lappend COMPONENTS [ list "GEN_MUX" "$OFM_PATH/comp/base/logic/mux" "FULL" ]
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# Files
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lappend MOD "$ENTITY_BASE/axis_vector2packet.vhd"

‎comp/axis_tools/flow/vector2packet/axis_vector2packet.vhd‎

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-- SPDX-License-Identifier: BSD-3-Clause
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-- Copyright (C) 2026 CESNET z. s. p. o.
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-- Author(s): Tomáš Neckař <xneckat00@stud.fit.vut.cz>
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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use work.math_pack.all;
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entity AXIS_VECTOR2PACKET is
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generic (
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-- width of RX Logic vector data signal in bits
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RX_TDATA_WIDTH : natural := 64;
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-- width of TX AXI-Stream data signal in bits - supported are only powers of 2
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TX_TDATA_WIDTH : natural := 64;
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-- width of TX AXI-Stream user signal in bits
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TUSER_WIDTH : natural := 64
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);
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port (
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-- =========================================================================
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-- Clock and reset signals
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-- =========================================================================
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CLK : in std_logic;
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RESET : in std_logic;
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-- =========================================================================
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-- RX Logic vector interface (CLK)
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-- =========================================================================
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RX_TDATA : in std_logic_vector(RX_TDATA_WIDTH-1 downto 0);
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RX_TUSER : in std_logic_vector(TUSER_WIDTH-1 downto 0);
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RX_TVALID : in std_logic;
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RX_TREADY : out std_logic;
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-- =========================================================================
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-- TX AXI-Stream interface (CLK)
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-- =========================================================================
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TX_TDATA : out std_logic_vector(TX_TDATA_WIDTH-1 downto 0);
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TX_TUSER : out std_logic_vector(TUSER_WIDTH-1 downto 0);
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TX_TKEEP : out std_logic_vector(TX_TDATA_WIDTH/8-1 downto 0);
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TX_TLAST : out std_logic;
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TX_TVALID : out std_logic;
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TX_TREADY : in std_logic
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);
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end entity;
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architecture FULL of AXIS_VECTOR2PACKET is
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constant PACKETS_PER_VECTOR : natural := div_roundup(RX_TDATA_WIDTH, TX_TDATA_WIDTH); -- (RX_TDATA_WIDTH + TX_TDATA_WIDTH - 1) / TX_TDATA_WIDTH;
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constant PADDED_WIDTH : natural := PACKETS_PER_VECTOR * TX_TDATA_WIDTH; -- PAD_BITS + RX_TDATA_WIDTH
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constant PAD_BITS : natural := PADDED_WIDTH - RX_TDATA_WIDTH; -- count of padding bits
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signal rx_data_padded : std_logic_vector(PADDED_WIDTH-1 downto 0); -- PAD_BITS & RX_TDATA_WIDTH
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signal full : std_logic; -- whether component has unsent data or not
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signal sel : unsigned(max(1,log2(PACKETS_PER_VECTOR))-1 downto 0) := (others => '0'); -- selects range to send from reg_data as a axis frame
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signal reg_data : std_logic_vector(PADDED_WIDTH-1 downto 0);
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signal reg_user : std_logic_vector(TUSER_WIDTH-1 downto 0);
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begin
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-- pad data so that the last frame isnt out of range
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padding_g: if PAD_BITS > 0 generate
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rx_data_padded <= std_logic_vector(to_unsigned(0, PAD_BITS)) & RX_TDATA;
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else generate
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rx_data_padded <= RX_TDATA;
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end generate;
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RX_TREADY <= not full;
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TX_TVALID <= full;
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-- the component is either ready to receive data or transmits valid data
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full_p : process (CLK)
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begin
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if (rising_edge(CLK)) then
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if (RESET = '1') then
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full <= '0';
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elsif (full = '0') then -- RX_TREADY = '1'
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if (RX_TVALID = '1') then
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-- if received valid data, set full (drives RX_TREADY low)
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full <= '1';
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end if;
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else -- TX_TVALID = '1'
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if (TX_TREADY = '1') then
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if (sel = PACKETS_PER_VECTOR - 1) then
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-- if sent last frame, clear full (drives RX_TREADY high)
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full <= '0';
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end if;
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end if;
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end if;
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end if;
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end process;
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-- load new data to registers when RX side ready and valid
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regs_p : process (CLK)
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begin
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if (rising_edge(CLK)) then
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if (RESET = '0') then
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if (RX_TREADY = '1' and RX_TVALID = '1') then
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reg_data <= rx_data_padded;
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reg_user <= RX_TUSER;
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end if;
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end if;
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end if;
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end process;
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-- if tx side ready, increments frame counter (sel) until last
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sel_p : process (CLK)
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begin
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if rising_edge(CLK) then
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if (RESET = '1') then
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sel <= (others => '0');
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elsif (full = '0') then -- RX_TREADY = '1'
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if (RX_TVALID = '1') then
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sel <= (others => '0');
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end if;
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else -- TX_TVALID = '1'
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if (TX_TREADY = '1') then
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if (sel < PACKETS_PER_VECTOR - 1) then
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sel <= sel + 1;
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end if;
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end if;
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end if;
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end if;
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end process;
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-- select range to send from reg_data as a axis frame
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mux_i : entity work.GEN_MUX
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generic map (
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DATA_WIDTH => TX_TDATA_WIDTH,
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MUX_WIDTH => PACKETS_PER_VECTOR
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) port map (
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DATA_IN => reg_data,
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SEL => std_logic_vector(sel),
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DATA_OUT => TX_TDATA
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);
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TX_TUSER <= reg_user;
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TX_TLAST <= '1' when (sel = PACKETS_PER_VECTOR - 1) else '0';
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tx_tkeep_p : process (sel)
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begin
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TX_TKEEP <= (others => '1');
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-- if last frame, mark fully padded bytes (as keep = 0)
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if (sel = PACKETS_PER_VECTOR - 1 and PAD_BITS >= 8) then
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TX_TKEEP(TX_TDATA_WIDTH / 8 - 1 downto (TX_TDATA_WIDTH - PAD_BITS - 1) / 8 + 1) <= (others => '0');
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end if;
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end process;
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end architecture;

‎comp/axis_tools/flow/vector2packet/readme.rst‎

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.. _axis_vector2packet:
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AXIS_VECTOR2PACKET
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------------
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It's recommended that TX_TDATA_WIDTH is a power of 2 and at least one byte.
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.. vhdl:autoentity:: AXIS_VECTOR2PACKET

‎comp/axis_tools/flow/vector2packet/synth/Makefile‎

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# SPDX-License-Identifier: BSD-3-Clause
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# Copyright (C) 2026 CESNET z. s. p. o.
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# Author(s): Tomáš Neckař <xneckat00@stud.fit.vut.cz>
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TOP_LEVEL_ENT=AXIS_VECTOR2PACKET
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SYNTH=quartus
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export DEVICE=AGILEX
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CLK_PORTS=CLK
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CLK_PERIOD=5.0
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.PHONY: all
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all: comp
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include ../../../../../build/Makefile

‎comp/axis_tools/flow/vector2packet/uvm/Modules.tcl‎

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# Copyright (C) 2026 CESNET z. s. p. o.
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# Author(s): Tomáš Neckař <xneckat00@stud.fit.vut.cz>
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# SPDX-License-Identifier: BSD-3-Clause
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lappend COMPONENTS [ list "SV_LV_AXI_BASE" "$OFM_PATH/comp/uvm/logic_vector_array_axi" "FULL"]
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lappend COMPONENTS [ list "SV_RESET_BASE" "$OFM_PATH/comp/uvm/reset" "FULL"]
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lappend MOD "$ENTITY_BASE/tbench/env/pkg.sv"
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lappend MOD "$ENTITY_BASE/tbench/test/pkg.sv"
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lappend MOD "$ENTITY_BASE/tbench/generic.sv"
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lappend MOD "$ENTITY_BASE/tbench/testbench.sv"

‎comp/axis_tools/flow/vector2packet/uvm/signals.fdo‎

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# Copyright (C) 2026 CESNET z. s. p. o.
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# Author(s): Tomáš Neckař <xneckat00@stud.fit.vut.cz>
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# SPDX-License-Identifier: BSD-3-Clause
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add wave -noupdate -group "RESET" "/testbench/reset/*"
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add wave -noupdate -group "RX" "/testbench/axi_rx/*"
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add wave -noupdate -group "TX" "/testbench/axi_tx/*"

‎comp/axis_tools/flow/vector2packet/uvm/tbench/env/config.sv‎

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// Copyright (C) 2026 CESNET z. s. p. o.
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// Author(s): Tomáš Neckař <xneckat00@stud.fit.vut.cz>
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// SPDX-License-Identifier: BSD-3-Clause
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class config_sequence extends uvm_object;
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`ndk_object_utils(uvm_vector2packet::config_sequence)
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int unsigned space_size_min = 0;
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int unsigned space_size_max = 200;
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int unsigned frame_size_min = 1;
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int unsigned frame_size_max = 1500;
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int unsigned rdy_probability_min = 10;
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int unsigned rdy_probability_max = 100;
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function new(string name = "uvm_vector2packet::config_sequence");
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super.new(name);
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endfunction
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endclass

‎comp/axis_tools/flow/vector2packet/uvm/tbench/env/env.sv‎

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// Copyright (C) 2026 CESNET z. s. p. o.
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// Author(s): Tomáš Neckař <xneckat00@stud.fit.vut.cz>
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// SPDX-License-Identifier: BSD-3-Clause
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class env #(
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int unsigned RX_ITEMS,
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int unsigned RX_ITEM_WIDTH,
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int unsigned TX_ITEMS,
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int unsigned TX_ITEM_WIDTH,
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int unsigned TUSER_WIDTH
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) extends uvm_env;
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`uvm_component_param_utils(uvm_vector2packet::env #(RX_ITEMS, RX_ITEM_WIDTH, TX_ITEMS, TX_ITEM_WIDTH, TUSER_WIDTH));
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// Virtual sequencer
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sequencer #(RX_ITEMS, RX_ITEM_WIDTH, TX_ITEMS, TX_ITEM_WIDTH, TUSER_WIDTH) m_sequencer;
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// RESET interface
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protected uvm_reset::agent m_reset;
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// RX environments
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protected uvm_axi::agent_rx #(RX_ITEMS, RX_ITEM_WIDTH, TUSER_WIDTH) m_rx;
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// TX environments
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protected uvm_axi::agent_tx #(TX_ITEMS, TX_ITEM_WIDTH, TUSER_WIDTH) m_tx;
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// Scoreboard
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protected scoreboard #(TX_ITEMS, TX_ITEM_WIDTH, TUSER_WIDTH) m_sc;
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// Model instance
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protected uvm_vector2packet::model #(RX_ITEMS, RX_ITEM_WIDTH, TX_ITEMS, TX_ITEM_WIDTH, TUSER_WIDTH) m_model;
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// Constructor
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function new(string name, uvm_component parent = null);
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super.new(name, parent);
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endfunction
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function int unsigned used();
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int unsigned ret = 0;
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ret |= (m_model.used() != 0);
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ret |= (m_sc.used() != 0);
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return ret;
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endfunction
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// Create base components of environment.
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function void build_phase(uvm_phase phase);
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uvm_reset::config_item m_cfg_reset;
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uvm_axi::config_item m_cfg_rx;
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uvm_axi::config_item m_cfg_tx;
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//Call parents function build_phase
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super.build_phase(phase);
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//Create reset environment
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m_cfg_reset = new;
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m_cfg_reset.active = UVM_ACTIVE; // Activly driven environment
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// interface register name have to be same in testbench uvm_config_db#(...)::set();
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m_cfg_reset.interface_name = "vif_reset";
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uvm_config_db #(uvm_reset::config_item)::set(this, "m_reset", "m_config", m_cfg_reset);
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// Creation of the reset
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m_reset = uvm_reset::agent::type_id::create("m_reset", this);
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// Configuration of the m_rx
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m_cfg_rx = new;
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m_cfg_rx.active = UVM_ACTIVE;
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// interface register name has to be same in testbench uvm_config_db#(...)::set();
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m_cfg_rx.interface_name = "vif_axi_rx";
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uvm_config_db #(uvm_axi::config_item)::set(this, "m_rx", "m_config", m_cfg_rx);
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// Creation of the m_rx
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m_rx = uvm_axi::agent_rx #(RX_ITEMS, RX_ITEM_WIDTH, TUSER_WIDTH)::type_id::create("m_rx", this);
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// Configuration of the m_tx
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m_cfg_tx = new;
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m_cfg_tx.active = UVM_ACTIVE;
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// interface register name has to be same in testbench uvm_config_db#(...)::set();
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m_cfg_tx.interface_name = "vif_axi_tx";
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uvm_config_db #(uvm_axi::config_item)::set(this, "m_tx", "m_config", m_cfg_tx);
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// Creation of the m_tx
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m_tx = uvm_axi::agent_tx #(TX_ITEMS, TX_ITEM_WIDTH, TUSER_WIDTH)::type_id::create("m_tx", this);
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// Create sequencer
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m_sequencer = sequencer #(
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RX_ITEMS, RX_ITEM_WIDTH, TX_ITEMS, TX_ITEM_WIDTH, TUSER_WIDTH
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)::type_id::create("m_sequencer", this);
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m_sc = scoreboard #(TX_ITEMS, TX_ITEM_WIDTH, TUSER_WIDTH)::type_id::create("m_sc", this);
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m_model = uvm_vector2packet::model #(
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RX_ITEMS, RX_ITEM_WIDTH, TX_ITEMS, TX_ITEM_WIDTH, TUSER_WIDTH
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)::type_id::create("m_model", this);
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endfunction
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// Connect agent's ports with ports from scoreboard.
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function void connect_phase(uvm_phase phase);
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// Connection of the reset
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//m_reset.sync_connect(m_rx.reset_sync);
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//m_reset.sync_connect(m_tx.reset_sync);
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// Connection to scoreboard
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m_rx.analysis_port.connect(m_model.m_rx.analysis_export);
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// Connect to Scoreboard
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m_model.m_tx.connect(m_sc.cmp.analysis_imp_model);
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m_tx.analysis_port.connect(m_sc.cmp.analysis_imp_dut);
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// Connect sequencer
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m_sequencer.m_reset = m_reset.m_sequencer;
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m_sequencer.m_rx = m_rx.m_sequencer;
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m_sequencer.m_tx = m_tx.m_sequencer;
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endfunction
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endclass

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