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๐Ÿ” Gate-Level Cybernetic Classifier

  • A feedback-driven adaptive learning binary-classifier that based on error input autonomously alters its decision boundary by implementing Max-Initialized Decremental Search (MIDS) and resets the control loop for repeated adaptive cycles.

Adaptive Learning Demonstration

๐Ÿค– Adaptive learning system implementing MIDS algorithm

โš™๏ธ Implementation Stack

Verilog Logisim Circuits

๐Ÿ› ๏ธ Toolchain

Icarus Verilog GTKWave Yosys VS Code

๐Ÿ“ˆ Planned Progression

  • Stage 0 (v0.x): Strict Boolean pattern relation analyzer. No learning, no noise tolerance, decision boundaries fixed by structural wiring.
  • Stage 1 (v1.0): Popcount based similarity and a variable threshold to alter the decision boundary. Introduces noise tolerance and ability to change the decision output without structural changes.
  • Stage 2 (v1.1): Cybernetic Feedback-driven adaptive learning. System alters its decision boundary based on external feedback to correct its decision output.

๐Ÿงฑ Versions Built

  • Version 0: A pattern relation analyzer that classifies how an input pattern relates to a stored pattern, enforces rule based recognition rather than learning.

    • Detector_v0.0 -> Recognizes the exact pattern and sub-patterns if they are inside the boundary set up by weights-grid.
    • Detector v0.1 -> Recognizes the exact pattern and super-patterns if they are outside the boundary set up by weights-grid.
    • Detector v0.2 -> Classifies the input as a sub-pattern, super-pattern, anti-pattern or equivalence precisely through a 2-POV logical analysis.
  • Version 1: Pop-count based judgement against a variable Threshold instead of perfect equivalence check and cybernetic feedback-driven adaptive learning.

    • Detector_v1.0 -> Recognizes the pattern if total number of matched pixels are greater than the set threshold which can vary giving us ability to control the decision output.
    • Detector_v1.1 -> A feedback-driven adaptive system that autonomously adjusts its decision boundary to correct its output, using algorithms optimized for hardware constraints.

Block-Diagram

๐Ÿงฉ Block Diagram - Detector_v1.0 (Manually Alterable Decision Boundary)

๐Ÿง  Adaptive Learning Algorithms

Property MIDS SATU
Correction Speed O(N) O(1)
State Awareness None Current & desired output
Direction Always starts from max, decrements Sets to M or M-1 as needed
Initialization Bias Instant correction for false positives None
Hardware Complexity Low - decrementer only Higher - decrementer + decision logic
Guaranteed Convergence Yes Yes

๐ŸŽฏ Convergence Proofs

Correction Speeds

โฑ๏ธ Correction Speed Complexity Comparison

๐Ÿ’ป Verilog Implementation

๐ŸŽฏ Strict Boolean Matching

Pattern Detector Output

Equivalence & Sub-Pattern Recognition ๐Ÿ”น

Pattern Detector Output

Equivalence & Super-Pattern Recognition ๐ŸŸฆ

Pattern Detector Output

Equivalence & Super & Sub & Anti-Pattern Recognition ๐Ÿ”น๐ŸŸฆ

๐Ÿ”„ Popcount-Based Adaptive Learning

Pattern Detector Output

Manually Alterable Decision Boundary โš–๏ธ

๐Ÿ”ฌ RTL Synthesis Results (Yosys)

To verify hardware realizability, all detector variants were synthesized using Yosys. The resulting gate-level netlists were analyzed to compare architectural complexity and resource utilization across the evolution of the Cybernetic Classifier.

๐Ÿ“Š RTL Synthesis Comparison

Version Module Cells Key Hardware Structures Purpose
Detector v0.0 Eq/Sub Recognizer 8 3 AND, 2 NOT, OR, Reduction-AND Recognizes exact matches and input sub-patterns of the reference pattern
Detector v0.1 Eq/Super Recognizer 8 3 AND, 2 NOT, OR, Reduction-AND Recognizes exact matches and input super-patterns of the reference pattern
Detector v0.2 Multi-POV Classifier 28 Dual Recognition Engines, Decision Logic, 11 MUXes Classifies input-reference relationships as SUB, SUPER, EQ, or ANTI
Detector v1.0 Pop-Count Recognition 22 15 Adders, Comparator, Threshold Logic Similarity-based recognition with a manually alterable decision boundary

๐Ÿ† Synthesis Highlights

Category Result
Smallest Design Eq/Sub Recognizer (8 cells)
Smallest Design Eq/Super Recognizer (8 cells)
Most Arithmetic-Heavy Pop-Count Recognition (15 adders)
Most Decision-Heavy Multi-POV Classifier (11 MUXes)
Largest Design Multi-POV Classifier (28 cells)

All detector variants were successfully synthesized using Yosys.

RTL-Synthesis

Detector_v1.0 Synthesized - Yosys โœ…

๐Ÿ› ๏ธCurrent Development:

  • Stage 2 in progress - MIDS: Developed โœ“ | SATU: In Development

โฌ‡๏ธ Download This Repository

๐ŸชŸ Windows

Download โ†’ download_repos.bat

Double-click it and pick the repo(s) you want.

๐Ÿง Linux / macOS

Download โ†’ download_repos.sh

bash

chmod +x download_repos.sh
./download_repos.sh

Always downloads the latest version.

๐Ÿ“œLicense

  • Source code and HDL files are licensed under the MIT License.
  • Documentation, diagrams, images, and PDFs are licensed under Creative Commons Attribution 4.0 (CC BY 4.0).

About

This project explores how adaptive behavior and learning-like dynamics can emerge from purely deterministic gate-level systems. It evolves from strict Boolean matching to score-based decision making, culminating in a cybernetic feedback-driven adaptive learning system ๐Ÿค–.

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