ccc: handle multiple continous CCCs

Author: kgugala

src/ctrl/ccc.sv

@@ -96,6 +96,7 @@ module ccc
     input logic ccc_valid_i,
 
     output logic done_fsm_o,
+    output logic next_ccc_o,
 
     // Bus Monitor interface
     input logic bus_start_det_i,
@@ -403,7 +404,7 @@ module ccc
     TxData,
     TxDataTbit,
     WaitForBusCond,
-    WaitForStop,
+    NextCCC,
     DoneCCC,
     HandleENTDAA,
     HandleTargetENTDAA,
@@ -576,7 +577,7 @@ module ccc
       end
       TxDirectAddrAck: begin
         if (bus_tx_done_i) begin
-          if (is_byte_rsvd_addr) state_d = WaitForStop;
+          if (is_byte_rsvd_addr) state_d = NextCCC;
           else if ((is_byte_our_addr || is_byte_virtual_addr) && command_rnw) state_d = TxData;
           else if ((is_byte_our_addr || is_byte_virtual_addr) && ~command_rnw) begin
             if (command_code == `I3C_DIRECT_SETXTIME) state_d = RxSubCmdByte;
@@ -610,8 +611,8 @@ module ccc
       WaitForBusCond: begin
         if (bus_rstart_det_i) state_d = RxDirectAddr;
       end
-      WaitForStop: begin
-        state_d = WaitForStop; // Bus stop always goes to DoneCCC
+      NextCCC: begin
+        state_d = WaitCCC; // Bus stop always goes to DoneCCC
       end
       DoneCCC: begin
         state_d = Idle;
@@ -632,6 +633,7 @@ module ccc
     ccc_tx_sel_od_pp = '0;
 
     done_fsm_o = '0;
+    next_ccc_o = '0;
     unique case (state_q)
       Idle: begin
 
@@ -692,6 +694,9 @@ module ccc
         ccc_tx_req_value = {7'h00, ~tx_data_done};
         ccc_tx_sel_od_pp = '1;
       end
+      NextCCC: begin
+        next_ccc_o = '1;
+      end
       DoneCCC: begin
         done_fsm_o = '1;
       end

src/ctrl/controller_standby_i3c.sv

@@ -247,6 +247,7 @@ module controller_standby_i3c
   logic [7:0] ccc;
   logic ccc_valid;
   logic is_ccc_done;
+  logic is_next_ccc;
   logic is_hotjoin_done;
 
   //
@@ -303,7 +304,7 @@ module controller_standby_i3c
         2'b10:   xfer_mux_sel <= Ibi;
         default: xfer_mux_sel <= Fsm;
       endcase
-    else if (xfer_mux_sel == Ccc && is_ccc_done) xfer_mux_sel <= Fsm;
+    else if ((xfer_mux_sel == Ccc && is_ccc_done) || (xfer_mux_sel == Ccc && is_next_ccc)) xfer_mux_sel <= Fsm;
     else if (xfer_mux_sel == Ibi && ibi_done) xfer_mux_sel <= Fsm;
   end
 
@@ -455,6 +456,7 @@ module controller_standby_i3c
       .ccc_o                      (ccc),
       .ccc_valid_o                (ccc_valid),
       .is_ccc_done_i              (is_ccc_done),
+      .is_next_ccc_i              (is_next_ccc),
       .is_hotjoin_done_i          (is_hotjoin_done),
       .last_addr_o                (bus_addr_o),
       .last_addr_valid_o          (bus_addr_valid_o),
@@ -475,6 +477,7 @@ module controller_standby_i3c
       .ccc_i                     (ccc),
       .ccc_valid_i               (ccc_valid),
       .done_fsm_o                (is_ccc_done),
+      .next_ccc_o                (is_next_ccc),
       .bus_start_det_i           (ctrl_bus_i.start_det),
       .bus_rstart_det_i          (ctrl_bus_i.rstart_det),
       .bus_stop_det_i            (ctrl_bus_i.stop_det),

src/ctrl/i3c_target_fsm.sv

@@ -109,6 +109,7 @@ module i3c_target_fsm #(
     output logic [7:0] ccc_o,
     output logic ccc_valid_o,
     input logic is_ccc_done_i,
+    input logic is_next_ccc_i,
 
     input logic is_hotjoin_done_i,
 
@@ -557,6 +558,7 @@ module i3c_target_fsm #(
 
       DoCCC: begin
         if (is_ccc_done_i) state_d = DoneCCC;
+        else if (is_next_ccc_i) state_d = RxSByte;
       end
       DoneCCC: begin
         state_d = Idle;

verification/cocotb/top/lib_i3c_top/test_ccc.py

@@ -90,7 +90,7 @@ async def test_ccc_setdasa(dut):
     await ClockCycles(tb.clk, 50)
     # set regular device dynamic address
     await i3c_controller.i3c_ccc_write(
-        ccc=CCC.DIRECT.SETDASA, directed_data=[(STATIC_ADDR, [DYNAMIC_ADDR << 1])]
+        ccc=CCC.DIRECT.SETDASA, directed_data=[(STATIC_ADDR, [DYNAMIC_ADDR << 1])], stop=False
     )
     # set virtual device dynamic address
     await i3c_controller.i3c_ccc_write(