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1 parent d3abb98 commit 45f40caCopy full SHA for 45f40ca
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verification/cocotb/top/lib_i3c_top/test_recovery.py
@@ -5389,7 +5389,7 @@ async def test_ri_read_interrupted_by_ccc(dut):
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# uncommented, the controller sends actual S + Addr+W + CMD + PEC + Sr, in that case
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# the recovery_receiver enters Error state and keeps RX Queue in soft reset state
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# which blocks it from receiving data sent to main target on I3C bus.
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- # await i3c_controller.take_bus_control()
+ await i3c_controller.take_bus_control()
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# Start RI write phase: S + Addr+W (to virtual target)
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await i3c_controller.send_start()
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