ibi: wait for stop or repeated start

Author: kgugala

src/ctrl/controller_standby_i3c.sv

@@ -579,6 +579,7 @@ module controller_standby_i3c
       .scl_posedge_i  (ctrl_bus_i.scl.pos_edge),
       .bus_available_i(bus_available),
       .bus_stop_i     (ctrl_bus_i.stop_det),
+      .bus_rstart_i   (ctrl_bus_i.rstart_det),
 
       .bus_tx_done_i     (ibi_bus_tx_done),
       .bus_tx_req_byte_o (ibi_bus_tx_req_byte),

src/ctrl/ibi.sv

@@ -44,6 +44,7 @@ module ibi (
     input logic scl_posedge_i,
     input logic bus_available_i,
     input logic bus_stop_i,
+    input logic bus_rstart_i,
 
     // Bus TX interface
     input logic bus_tx_done_i,
@@ -105,7 +106,7 @@ module ibi (
     // Transmitt T bit
     SendTbit,
     // Wait for stop condition
-    WaitStop,
+    WaitStopOrRstart,
     // Flush remaining IBI data bytes
     Flush,
     // Signal to primary FSM that IBI is done
@@ -144,7 +145,7 @@ module ibi (
         if (bus_stop_i) state_q <= Done;
         else if (bus_rx_done_i)
           if (bus_rx_req_nack)  // NACK
-            state_q <= WaitStop;
+            state_q <= WaitStopOrRstart;
           else  // ACK
             state_q <= WaitForSclNegedgeAfterAck;
 
@@ -159,7 +160,7 @@ module ibi (
         if (bus_stop_i) state_q <= Flush;
         else if (bus_tx_done_i) state_q <= ibi_byte_last_i ? Done : SendData;
 
-        WaitStop: if (bus_stop_i) state_q <= Idle;
+        WaitStopOrRstart: if (bus_stop_i | bus_rstart_i) state_q <= Idle;
 
         Flush: if (!ibi_byte_valid_i) state_q <= Done;
 
@@ -273,6 +274,6 @@ module ibi (
   assign done_o = (state_q == Done);
 
   assign ibi_status_o    = ibi_status;
-  assign ibi_status_we_o = (state_q == Done) | ((state_q == WaitStop) & bus_stop_i);
+  assign ibi_status_we_o = (state_q == Done) | ((state_q == WaitStopOrRstart) & bus_stop_i);
 
 endmodule