test.sus_errors.txt

[INFO  sus_compiler::compiler_top] Selecting all parameter-less modules as --top
[INFO  sus_compiler::instantiation::instantiator] Instantiated IntToBool #()
[INFO  sus_compiler::instantiation::instantiator] Instantiated BoolToInt #()
[INFO  sus_compiler::instantiation::instantiator] Instantiated example_md #()
[INFO  sus_compiler::instantiation::instantiator] Instantiated multiply_add #()
[INFO  sus_compiler::instantiation::instantiator] Instantiated pow17 #()
[INFO  sus_compiler::instantiation::instantiator] Instantiated test_pow17 #()
[INFO  sus_compiler::instantiation::instantiator] Instantiated fibonnaci #()
[INFO  sus_compiler::instantiation::instantiator] Instantiated blur2 #()
[INFO  sus_compiler::instantiation::instantiator] Instantiated Tree_Multiply #()
[INFO  sus_compiler::instantiation::instantiator] Instantiated Accumulator #()
[INFO  sus_compiler::instantiation::instantiator] Instantiated blur #()
[INFO  sus_compiler::instantiation::instantiator] Instantiated Unpack4 #()
[ERROR sus_compiler::instantiation::instantiator] Failed to instantiate generative #()
[INFO  sus_compiler::instantiation::instantiator] Instantiated add_indices_to_array #()
[ERROR sus_compiler::instantiation::instantiator] Failed to instantiate assignment_producer #()
[ERROR sus_compiler::instantiation::instantiator] Failed to instantiate test_various_assignments #()
[INFO  sus_compiler::instantiation::instantiator] Instantiated first_bit_idx_6 #()
[ERROR sus_compiler::instantiation::instantiator] Failed to instantiate multiply_add_with_latencies #()
[ERROR sus_compiler::instantiation::instantiator] Failed to instantiate first_bit_idx_24 #()
[ERROR sus_compiler::instantiation::instantiator] Failed to instantiate permute #()
[ERROR sus_compiler::instantiation::instantiator] Failed to instantiate permute24 #()
[INFO  sus_compiler::instantiation::instantiator] Instantiated test_single_wire #()
[ERROR sus_compiler::instantiation::instantiator] Failed to instantiate disjoint_ports #()
[ERROR sus_compiler::instantiation::instantiator] Failed to instantiate undeteriminable_input_latency #()
[INFO  sus_compiler::instantiation::instantiator] Instantiated specified_input_latency #()
[INFO  sus_compiler::instantiation::instantiator] Instantiated determinable_input_latency #()
[INFO  sus_compiler::instantiation::instantiator] Instantiated determinable_because_no_input_output_ports #()
[ERROR sus_compiler::instantiation::instantiator] Failed to instantiate conflicting_latency_declarations #()
[ERROR sus_compiler::instantiation::instantiator] Failed to instantiate bad_cycle #()
[INFO  sus_compiler::instantiation::instantiator] Instantiated module_taking_time #()
[INFO  sus_compiler::instantiation::instantiator] Instantiated matrix_vector_mul #()
[ERROR sus_compiler::instantiation::instantiator] Failed to instantiate bad_cycle2 #()
[INFO  sus_compiler::instantiation::instantiator] Instantiated module_taking_a_lot_of_time #()
[INFO  sus_compiler::instantiation::instantiator] Instantiated good_cycle #()
[INFO  sus_compiler::instantiation::instantiator] Instantiated input_only #()
[INFO  sus_compiler::instantiation::instantiator] Instantiated multiple_inputs_only #()
[INFO  sus_compiler::instantiation::instantiator] Instantiated output_only #()
[INFO  sus_compiler::instantiation::instantiator] Instantiated multiple_outputs_only #()
[INFO  sus_compiler::instantiation::instantiator] Instantiated submodule #()
[INFO  sus_compiler::instantiation::instantiator] Instantiated doNothing #()
[ERROR sus_compiler::instantiation::instantiator] Failed to instantiate contains_submodule_submodule #()
[INFO  sus_compiler::instantiation::instantiator] Instantiated xor #()
[INFO  sus_compiler::instantiation::instantiator] Instantiated use_xor #()
[INFO  sus_compiler::instantiation::instantiator] Instantiated fizz_buzz #()
[INFO  sus_compiler::instantiation::instantiator] Instantiated mbf_dual #()
[INFO  sus_compiler::instantiation::instantiator] Instantiated monotonize_down #()
[INFO  sus_compiler::instantiation::instantiator] Instantiated my_mod #()
[INFO  sus_compiler::instantiation::instantiator] Instantiated use_my_mod #()
[INFO  sus_compiler::instantiation::instantiator] Instantiated submodule_named_ports #()
[ERROR sus_compiler::instantiation::instantiator] Failed to instantiate use_submodule_named_ports #()
[ERROR sus_compiler::instantiation::instantiator] Failed to instantiate contains_submodule_submodule #()
[INFO  sus_compiler::instantiation::instantiator] Instantiated cross_bool #()
[INFO  sus_compiler::instantiation::instantiator] Instantiated cross_int #()
[INFO  sus_compiler::instantiation::instantiator] Instantiated cross_memory #()
[INFO  sus_compiler::instantiation::instantiator] Instantiated offset_backwards #()
[ERROR sus_compiler::instantiation::instantiator] Failed to instantiate dual_port_mem #()
[ERROR sus_compiler::instantiation::instantiator] Failed to instantiate use_fifo #()
[ERROR sus_compiler::instantiation::instantiator] Failed to instantiate test_separated_domain #()
[INFO  sus_compiler::instantiation::instantiator] Instantiated no_port_module #()
[ERROR sus_compiler::instantiation::instantiator] Failed to instantiate use_no_input_module #()
[INFO  sus_compiler::instantiation::instantiator] Instantiated mod_with_unused_interface #()
[ERROR sus_compiler::instantiation::instantiator] Failed to instantiate test_write_to_gen_var #()
[ERROR sus_compiler::instantiation::instantiator] Failed to instantiate use_bad_interface #()
[ERROR sus_compiler::instantiation::instantiator] Failed to instantiate sequenceDownFrom #()
[ERROR sus_compiler::instantiation::instantiator] Failed to instantiate sumUpTo #()
[ERROR sus_compiler::instantiation::instantiator] Failed to instantiate use_test #()
[INFO  sus_compiler::instantiation::instantiator] Instantiated tinyTestMod #(beep: 3)
[INFO  sus_compiler::instantiation::instantiator] Instantiated tinyTestMod #(beep: 4)
[INFO  sus_compiler::instantiation::instantiator] Instantiated testTinyTestMod #()
[ERROR sus_compiler::instantiation::instantiator] Failed to instantiate tree_add #(WIDTH: 1)
[ERROR sus_compiler::instantiation::instantiator] Failed to instantiate tree_add #(WIDTH: 3)
[ERROR sus_compiler::instantiation::instantiator] Failed to instantiate tree_add #(WIDTH: 7)
[ERROR sus_compiler::instantiation::instantiator] Failed to instantiate tree_add #(WIDTH: 15)
[ERROR sus_compiler::instantiation::instantiator] Failed to instantiate tree_add #(WIDTH: 31)
[ERROR sus_compiler::instantiation::instantiator] Failed to instantiate tree_add #(WIDTH: 63)
[ERROR sus_compiler::instantiation::instantiator] Failed to instantiate tree_add #(WIDTH: 127)
[ERROR sus_compiler::instantiation::instantiator] Failed to instantiate tree_add #(WIDTH: 255)
[ERROR sus_compiler::instantiation::instantiator] Failed to instantiate make_tree_add #()
[INFO  sus_compiler::instantiation::instantiator] Instantiated replicate #(T: type int #(FROM: 3, TO: 4), NUM_REPLS: 30)
[ERROR sus_compiler::instantiation::instantiator] Failed to instantiate use_replicate #()
[INFO  sus_compiler::instantiation::instantiator] Instantiated permute_t #(T: type int #(FROM: 1, TO: 8), SIZE: 8, SOURCES: [3, 2, 4, 5, 1, 2, 7, 6])
[INFO  sus_compiler::instantiation::instantiator] Instantiated use_permute #()
[INFO  sus_compiler::instantiation::instantiator] Instantiated instruction_decoder #()
[ERROR sus_compiler::instantiation::instantiator] Failed to instantiate run_instruction #()
[INFO  sus_compiler::instantiation::instantiator] Instantiated no_main_interface #()
[ERROR sus_compiler::instantiation::instantiator] Failed to instantiate use_no_main_interface #()
[ERROR sus_compiler::instantiation::instantiator] Failed to instantiate moduleWithBadDeclaration #()
[ERROR sus_compiler::instantiation::instantiator] Failed to instantiate moduleWithBadInterface #()
[ERROR sus_compiler::instantiation::instantiator] Failed to instantiate useModuleWithBadInterface #()
[ERROR sus_compiler::instantiation::instantiator] Failed to instantiate m #()
[ERROR sus_compiler::instantiation::instantiator] Failed to instantiate xyz #()
[INFO  sus_compiler::instantiation::instantiator] Instantiated TreeAdd #(WIDTH: 1, FROM: 3, TO: 4)
[INFO  sus_compiler::instantiation::instantiator] Instantiated TreeAdd #(WIDTH: 2, FROM: 3, TO: 4)
[INFO  sus_compiler::instantiation::instantiator] Instantiated TreeAdd #(WIDTH: 3, FROM: 3, TO: 4)
[INFO  sus_compiler::instantiation::instantiator] Instantiated TreeAdd #(WIDTH: 5, FROM: 3, TO: 4)
[INFO  sus_compiler::instantiation::instantiator] Instantiated numbersToAddUp #()
[INFO  sus_compiler::instantiation::instantiator] Instantiated sized_int_add #(LEFT_SIZE: 4, RIGHT_SIZE: 3, OUTPUT_SIZE: 5)
[INFO  sus_compiler::instantiation::instantiator] Instantiated use_sized_int_add #()
[ERROR sus_compiler::instantiation::instantiator] Failed to instantiate implicit_domain_forbidden #()
[ERROR sus_compiler::instantiation::instantiator] Failed to instantiate conflicting_domain_with_port_name #()
[ERROR sus_compiler::instantiation::instantiator] Failed to instantiate make_infinite_type #()
[ERROR sus_compiler::instantiation::instantiator] Failed to instantiate UseDualPortMem #()
[ERROR sus_compiler::instantiation::instantiator] Failed to instantiate example_FIFO #()
[ERROR sus_compiler::instantiation::instantiator] Failed to instantiate use_Iterator #()
[ERROR sus_compiler::instantiation::instantiator] Failed to instantiate UseBuiltinConstants #()
[ERROR sus_compiler::instantiation::instantiator] Failed to instantiate FailingAssert #()
[ERROR sus_compiler::instantiation::instantiator] Failed to instantiate latency_counting_disjoint_blocks #()
[ERROR sus_compiler::instantiation::instantiator] Failed to instantiate latency_counting_disjoint_blocks_merge_error #()
[ERROR sus_compiler::instantiation::instantiator] Failed to instantiate use_infer_me #()
[INFO  sus_compiler::instantiation::instantiator] Instantiated infer_me #(A: 5)
[INFO  sus_compiler::instantiation::instantiator] Instantiated infer_from_local_context #()
[INFO  sus_compiler::instantiation::instantiator] Instantiated LatencyOffset #(T: type bool #(), OFFSET: -9)
[INFO  sus_compiler::instantiation::instantiator] Instantiated ToBits #(T: type int #(FROM: 0, TO: 6))
[INFO  sus_compiler::instantiation::instantiator] Instantiated FromBits #(T: type int #(FROM: 0, TO: 6))
[INFO  sus_compiler::instantiation::instantiator] Instantiated FIFO #(T: type int #(FROM: 0, TO: 6), DEPTH: 30, MAY_PUSH_LATENCY: 8)
[INFO  sus_compiler::instantiation::instantiator] Instantiated instantiate_fifo #()
[INFO  sus_compiler::instantiation::instantiator] Instantiated infer_me #(A: 2)
[ERROR sus_compiler::instantiation::instantiator] Failed to instantiate inference_edge_case #()
[INFO  sus_compiler::instantiation::instantiator] Instantiated specified_latencies_not_ports_edge_case #()
[INFO  sus_compiler::instantiation::instantiator] Instantiated testArrayWrite #()
[ERROR sus_compiler::instantiation::instantiator] Failed to instantiate instantiate_infer_me_with_poison_output #()
[ERROR sus_compiler::instantiation::instantiator] Failed to instantiate use_MultiStateLoop #()
[ERROR sus_compiler::instantiation::instantiator] Failed to instantiate CombineArray #()
[ERROR sus_compiler::instantiation::instantiator] Failed to instantiate useUnknownLatency #()
[ERROR sus_compiler::instantiation::instantiator] Failed to instantiate use_infer_me_conflicting_directions #()
[INFO  sus_compiler::instantiation::instantiator] Instantiated infer_me_with_delta #(V: -31)
[INFO  sus_compiler::instantiation::instantiator] Instantiated use_infer_me_with_delta #()
[INFO  sus_compiler::instantiation::instantiator] Instantiated infer_me_with_negative_delta #(V: 31)
[INFO  sus_compiler::instantiation::instantiator] Instantiated use_infer_me_with_negative_delta #()
[ERROR sus_compiler::instantiation::instantiator] Failed to instantiate use_infer_me_inputs_only #()
[ERROR sus_compiler::instantiation::instantiator] Failed to instantiate use_ranks #()
[INFO  sus_compiler::instantiation::instantiator] Instantiated testInts #()
[ERROR sus_compiler::instantiation::instantiator] Failed to instantiate use_FIFO #()
[ERROR sus_compiler::instantiation::instantiator] Failed to instantiate write_to_generative_through_when #()
[INFO  sus_compiler::instantiation::instantiator] Instantiated ToBits #(T: type bool #()[60])
[ERROR sus_compiler::instantiation::instantiator] Failed to instantiate InstantiateTransmutes #()
[INFO  sus_compiler::instantiation::instantiator] Instantiated ToBits #(T: type int #(FROM: 0, TO: 255)[2])
[INFO  sus_compiler::instantiation::instantiator] Instantiated FromBits #(T: type int #(FROM: 0, TO: 65536))
[INFO  sus_compiler::instantiation::instantiator] Instantiated Transmute #(T1: type int #(FROM: 0, TO: 255)[2], T2: type int #(FROM: 0, TO: 65536))
[ERROR sus_compiler::instantiation::instantiator] Failed to instantiate StraightTransmute #()
[INFO  sus_compiler::instantiation::instantiator] Instantiated use_trigger #()
[INFO  sus_compiler::instantiation::instantiator] Instantiated use_use_trigger #()
[ERROR sus_compiler::instantiation::instantiator] Failed to instantiate testSlicing #()
[ERROR sus_compiler::instantiation::instantiator] Failed to instantiate wrong_slice_length #()
[ERROR sus_compiler::instantiation::instantiator] Failed to instantiate negative_slice #()
[INFO  sus_compiler::instantiation::instantiator] Instantiated multi_slice #()
[INFO  sus_compiler::instantiation::instantiator] Instantiated multi_slice_reverse #()
[ERROR sus_compiler::instantiation::instantiator] Failed to instantiate duplicate_port_names #()
[INFO  sus_compiler::instantiation::instantiator] Instantiated float_literal #()
[INFO  sus_compiler::instantiation::instantiator] Instantiated check_non_inlineds #()
[ERROR sus_compiler::instantiation::instantiator] Failed to instantiate make_when #()
[ERROR sus_compiler::instantiation::instantiator] Failed to instantiate use_make_when #()
[INFO  sus_compiler::instantiation::instantiator] Instantiated Repeat #(T: type bool #(), SIZE: 1)
[INFO  sus_compiler::instantiation::instantiator] Instantiated Repeat #(T: type bool #(), SIZE: 2)
[INFO  sus_compiler::instantiation::instantiator] Instantiated Repeat #(T: type bool #(), SIZE: 3)
[INFO  sus_compiler::instantiation::instantiator] Instantiated test_vivado_bug #()
[INFO  sus_compiler::instantiation::instantiator] Instantiated boolean_array_literals #()
[INFO  sus_compiler::instantiation::instantiator] Instantiated floats_and_doubles #()
[ERROR sus_compiler::instantiation::instantiator] Failed to instantiate use_module_taking_strings #()
[INFO  sus_compiler::instantiation::instantiator] Instantiated UIntToBits #(NUM_BITS: 0)
[INFO  sus_compiler::instantiation::instantiator] Instantiated zero_sized_stuffs #()
[INFO  sus_compiler::instantiation::instantiator] Instantiated test_all_modulos #()
[INFO  sus_compiler::instantiation::instantiator] Instantiated testShifts #()
[INFO  sus_compiler::instantiation::instantiator] Instantiated testRemainder #()
[INFO  sus_compiler::instantiation::instantiator] Instantiated ModuleWithInitialStates #()
[INFO  sus_compiler::instantiation::instantiator] Instantiated TestGenArrayOps #()
[ERROR sus_compiler::instantiation::instantiator] Failed to instantiate NonGenerativeSliceBoundsMustNotICE #()
[ERROR sus_compiler::instantiation::instantiator] Failed to instantiate InstantiatesItself #()
[INFO  sus_compiler::instantiation::instantiator] Instantiated ReceiveZerosArray #()
[INFO  sus_compiler::instantiation::instantiator] Instantiated TestZerosArrays #()
[ERROR sus_compiler::instantiation::instantiator] Failed to instantiate TestUnknownArraySize #()
[ERROR sus_compiler::instantiation::instantiator] Failed to instantiate TestNextPow2 #()
[INFO  sus_compiler::instantiation::instantiator] Instantiated TestSplits #()
[INFO  sus_compiler::instantiation::instantiator] Instantiated CountBitsWithSplits #()
[INFO  sus_compiler::instantiation::instantiator] Instantiated ModWithDomains #()
[INFO  sus_compiler::instantiation::instantiator] Instantiated UseModWithDomains #()
[ERROR sus_compiler::instantiation::instantiator] Failed to instantiate GenerativeCannotHaveLatencyDeclaration #()
[ERROR sus_compiler::instantiation::instantiator] Failed to instantiate try_conflicting_latencies #()
[ERROR sus_compiler::instantiation::instantiator] Failed to instantiate AssignUnset #()
[ERROR sus_compiler::instantiation::instantiator] Failed to instantiate ReadUnsetArrayElem #()
[ERROR sus_compiler::instantiation::instantiator] Failed to instantiate RegressionForBadPort #()
[INFO  sus_compiler::instantiation::instantiator] Instantiated IntNarrow #(FROM_I: 5, TO_I: 6, FROM: 0, TO: 1)
[INFO  sus_compiler::instantiation::instantiator] Instantiated IntNarrow #(FROM_I: 0, TO_I: 1, FROM: -3, TO: 6)
[INFO  sus_compiler::instantiation::instantiator] Instantiated IntNarrowToZero #()
[INFO  sus_compiler::instantiation::instantiator] Instantiated NegativeIntLiterals #()
[ERROR sus_compiler::instantiation::instantiator] Failed to instantiate WeirdlyNamedClock #()
[INFO  sus_compiler::instantiation::instantiator] Instantiated TwoDomainsWithLatRegs #()
[INFO  sus_compiler::instantiation::instantiator] Instantiated LatencyOffset #(T: type bool #(), OFFSET: 3)
[INFO  sus_compiler::instantiation::instantiator] Instantiated LatencyOffset #(T: type bool #(), OFFSET: -3)
[INFO  sus_compiler::instantiation::instantiator] Instantiated PositiveAndNegativeLatencyOffset #()
Warning: Clock 'Unconnected_clock_1' has no driver. Non-input clocks require exactly one driving submodule. Defaulting to 'clk'
    ╭─[ test.sus:26:6 ]
    │
 26 │     int a = pow17(2)
    │         ┬  
    │         ╰── Clock 'Unconnected_clock_1' has no driver. Non-input clocks require exactly one driving submodule. Defaulting to 'clk'
────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
    ╭─[ test.sus:26:6 ]
    │
 26 │     int a = pow17(2)
    │         ┬  
    │         ╰── Unused Variable: This variable does not affect the output ports of this module
────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
    ╭─[ test.sus:60:10 ]
    │
 60 │     gen int a
    │             ┬  
    │             ╰── Unused Variable: This variable does not affect the output ports of this module
────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
    ╭─[ test.sus:62:11 ]
    │
 62 │     gen bool b = true
    │              ┬  
    │              ╰── Unused Variable: This variable does not affect the output ports of this module
────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
    ╭─[ test.sus:63:11 ]
    │
 63 │     gen bool bb = false
    │              ─┬  
    │               ╰── Unused Variable: This variable does not affect the output ports of this module
────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
     ╭─[ test.sus:115:10 ]
     │
 115 │     gen int A = 1
     │             ┬  
     │             ╰── Unused Variable: This variable does not affect the output ports of this module
─────╯
Warning: Not Instantiating generative #() due to abstract typing errors
     ╭─[ test.sus:141:8 ]
     │
 141 │ module generative {
     │        ─────┬────  
     │             ╰────── Not Instantiating generative #() due to abstract typing errors
─────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
     ╭─[ test.sus:144:13 ]
     │
 144 │     gen int[x] ys
     │                ─┬  
     │                 ╰── Unused Variable: This variable does not affect the output ports of this module
─────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
     ╭─[ test.sus:148:13 ]
     │
 148 │     gen int[3] ps
     │                ─┬  
     │                 ╰── Unused Variable: This variable does not affect the output ports of this module
─────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
     ╭─[ test.sus:155:13 ]
     │
 155 │     gen int[3] xx = a
     │                ─┬  
     │                 ╰── Unused Variable: This variable does not affect the output ports of this module
─────╯
Error: 'i' is read-only
     ╭─[ test.sus:159:11 ]
     │
 159 │     if test {i = 5}
     │              ┬  
     │              ╰── 'i' is read-only
     │
     ├─[ test.sus:159:11 ]
     │
 142 │     interface generative : int#(FROM: 0, TO: 100) i -> int o, int o2
     │                                                   ┬  
     │                                                   ╰── 'i' declared here
─────╯
Error: Some parameters of 'v' were still unknown: int #(FROM: ?, TO: ?)
     ╭─[ test.sus:175:44 ]
     │
 175 │     interface assignment_producer : -> int v'0, int o'0, bool j'0 }
     │                                            ┬  
     │                                            ╰── Some parameters of 'v' were still unknown: int #(FROM: ?, TO: ?)
─────╯
Error: Some parameters of 'o' were still unknown: int #(FROM: ?, TO: ?)
     ╭─[ test.sus:175:53 ]
     │
 175 │     interface assignment_producer : -> int v'0, int o'0, bool j'0 }
     │                                                     ┬  
     │                                                     ╰── Some parameters of 'o' were still unknown: int #(FROM: ?, TO: ?)
─────╯
Warning: Clock 'Unconnected_clock_1' has no driver. Non-input clocks require exactly one driving submodule. Defaulting to 'clk'
     ╭─[ test.sus:178:15 ]
     │
 178 │     state int[3] st
     │                  ─┬  
     │                   ╰── Clock 'Unconnected_clock_1' has no driver. Non-input clocks require exactly one driving submodule. Defaulting to 'clk'
─────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
     ╭─[ test.sus:178:15 ]
     │
 178 │     state int[3] st
     │                  ─┬  
     │                   ╰── Unused Variable: This variable does not affect the output ports of this module
─────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
     ╭─[ test.sus:179:7 ]
     │
 179 │     bool b
     │          ┬  
     │          ╰── Unused Variable: This variable does not affect the output ports of this module
─────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
     ╭─[ test.sus:180:10 ]
     │
 180 │     reg int a, st[2], reg reg b = assignment_producer()
     │             ┬  
     │             ╰── Unused Variable: This variable does not affect the output ports of this module
─────╯
Warning: Not Instantiating multiply_add_with_latencies #() due to abstract typing errors
     ╭─[ test.sus:217:8 ]
     │
 217 │ module multiply_add_with_latencies {
     │        ─────────────┬─────────────  
     │                     ╰─────────────── Not Instantiating multiply_add_with_latencies #() due to abstract typing errors
─────╯
Error: A function call expects this to be an interface, but whatever it was the typechecker couldn't resolve
     ╭─[ test.sus:219:17 ]
     │
 219 │     int tmp'1 = multiply(a, b)
     │                 ────┬───  
     │                     ╰───── A function call expects this to be an interface, but whatever it was the typechecker couldn't resolve
─────╯
Error: No Global 'multiply' was found.
     ╭─[ test.sus:219:17 ]
     │
 219 │     int tmp'1 = multiply(a, b)
     │                 ────┬───  
     │                     ╰───── No Global 'multiply' was found.
─────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
     ╭─[ test.sus:224:43 ]
     │
 224 │     interface first_bit_idx_24 : bool[24] bits -> int first
     │                                           ──┬─  
     │                                             ╰─── Unused Variable: This variable does not affect the output ports of this module
─────╯
Error: Some parameters of 'first' were still unknown: int #(FROM: ?, TO: ?)
     ╭─[ test.sus:224:55 ]
     │
 224 │     interface first_bit_idx_24 : bool[24] bits -> int first
     │                                                       ──┬──  
     │                                                         ╰──── Some parameters of 'first' were still unknown: int #(FROM: ?, TO: ?)
─────╯
Error: This port is not strongly connected to the strongly connected port cluster 'bits'.
An input and output port are strongly connected if there is a direct dependency path from the input port to the output port.
Strongly connected ports are also transitive.
If you do not wish to change your design, then 'virtually' connect this port to the strongly connected cluster by explicitly annotating its absolute latency.
     ╭─[ test.sus:224:55 ]
     │
 224 │     interface first_bit_idx_24 : bool[24] bits -> int first
     │                                           ──┬─        ──┬──  
     │                                             ╰──────────────── 'bits' declared here
     │                                                         │    
     │                                                         ╰──── This port is not strongly connected to the strongly connected port cluster 'bits'.
An input and output port are strongly connected if there is a direct dependency path from the input port to the output port.
Strongly connected ports are also transitive.
If you do not wish to change your design, then 'virtually' connect this port to the strongly connected cluster by explicitly annotating its absolute latency.
─────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
     ╭─[ test.sus:225:9 ]
     │
 225 │     int[4] offsets
     │            ───┬───  
     │               ╰───── Unused Variable: This variable does not affect the output ports of this module
─────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
     ╭─[ test.sus:226:10 ]
     │
 226 │     bool[4] was_nonzeros
     │             ──────┬─────  
     │                   ╰─────── Unused Variable: This variable does not affect the output ports of this module
─────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
     ╭─[ test.sus:228:10 ]
     │
 228 │     for int i in 0..4 {
     │             ┬  
     │             ╰── Unused Variable: This variable does not affect the output ports of this module
─────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
     ╭─[ test.sus:229:11 ]
     │
 229 │        bool[6] these_bits
     │                ─────┬────  
     │                     ╰────── Unused Variable: This variable does not affect the output ports of this module
─────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
     ╭─[ test.sus:230:11 ]
     │
 230 │        for int j in 0..6 {
     │                ┬  
     │                ╰── Unused Variable: This variable does not affect the output ports of this module
─────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
     ╭─[ test.sus:234:7 ]
     │
 234 │        int offset, bool was_nonzero = first_bit_idx_6(these_bits)
     │            ───┬──  
     │               ╰──── Unused Variable: This variable does not affect the output ports of this module
─────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
     ╭─[ test.sus:234:20 ]
     │
 234 │        int offset, bool was_nonzero = first_bit_idx_6(these_bits)
     │                         ─────┬─────  
     │                              ╰─────── Unused Variable: This variable does not affect the output ports of this module
─────╯
Error: This port is not strongly connected to the strongly connected port cluster 'mbf', 'permuted_mbf'.
An input and output port are strongly connected if there is a direct dependency path from the input port to the output port.
Strongly connected ports are also transitive.
If you do not wish to change your design, then 'virtually' connect this port to the strongly connected cluster by explicitly annotating its absolute latency.
     ╭─[ test.sus:241:63 ]
     │
 241 │     interface permute : bool[128] mbf, int#(FROM: 0, TO: 100) selected_permutation -> bool[128] permuted_mbf
     │                                   ─┬─                         ──────────┬─────────              ──────┬─────  
     │                                    ╰────────────────────────────────────────────────────────────────────────── 'mbf' declared here
     │                                                                         │                             │       
     │                                                                         ╰───────────────────────────────────── This port is not strongly connected to the strongly connected port cluster 'mbf', 'permuted_mbf'.
An input and output port are strongly connected if there is a direct dependency path from the input port to the output port.
Strongly connected ports are also transitive.
If you do not wish to change your design, then 'virtually' connect this port to the strongly connected cluster by explicitly annotating its absolute latency.
     │                                                                                                       │       
     │                                                                                                       ╰─────── 'permuted_mbf' declared here
─────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
     ╭─[ test.sus:241:63 ]
     │
 241 │     interface permute : bool[128] mbf, int#(FROM: 0, TO: 100) selected_permutation -> bool[128] permuted_mbf
     │                                                               ──────────┬─────────  
     │                                                                         ╰─────────── Unused Variable: This variable does not affect the output ports of this module
─────╯
Warning: Not Instantiating permute24 #() due to abstract typing errors
     ╭─[ test.sus:247:8 ]
     │
 247 │ module permute24 {
     │        ────┬────  
     │            ╰────── Not Instantiating permute24 #() due to abstract typing errors
─────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
     ╭─[ test.sus:248:37 ]
     │
 248 │     interface permute24 : bool[128] mbf, bool[24] valid_permutes, bool start -> bool[128] permuted_out, bool permuted_out_valid
     │                                     ─┬─  
     │                                      ╰─── Unused Variable: This variable does not affect the output ports of this module
─────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
     ╭─[ test.sus:248:51 ]
     │
 248 │     interface permute24 : bool[128] mbf, bool[24] valid_permutes, bool start -> bool[128] permuted_out, bool permuted_out_valid
     │                                                   ───────┬──────  
     │                                                          ╰──────── Unused Variable: This variable does not affect the output ports of this module
─────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
     ╭─[ test.sus:248:72 ]
     │
 248 │     interface permute24 : bool[128] mbf, bool[24] valid_permutes, bool start -> bool[128] permuted_out, bool permuted_out_valid
     │                                                                        ──┬──  
     │                                                                          ╰──── Unused Variable: This variable does not affect the output ports of this module
─────╯
Error: Typing Error: writing the output of this expression expects 'int #(FROM: _, TO: _)' but was given 'bool #()[]'
     ╭─[ test.sus:250:2 ]
     │
 250 │     state bool[24] stored_valid_permutes = 000000000000000000000000
     │     ──────────────────┬─────────────────  
     │                       ╰─────────────────── Typing Error: writing the output of this expression expects 'int #(FROM: _, TO: _)' but was given 'bool #()[]'
─────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
     ╭─[ test.sus:252:10 ]
     │
 252 │     gen int aaaaa = 5
     │             ──┬──  
     │               ╰──── Unused Variable: This variable does not affect the output ports of this module
─────╯
Error: A function call expects this to be an interface, but found a regular wire
     ╭─[ test.sus:267:2 ]
     │
 267 │     aaaaa()
     │     ──┬──  
     │       ╰──── A function call expects this to be an interface, but found a regular wire
─────╯
Error: This port is not strongly connected to the strongly connected port cluster 'a', 'b', 'result'.
An input and output port are strongly connected if there is a direct dependency path from the input port to the output port.
Strongly connected ports are also transitive.
If you do not wish to change your design, then 'virtually' connect this port to the strongly connected cluster by explicitly annotating its absolute latency.
     ╭─[ test.sus:278:107 ]
     │
 278 │     interface disjoint_ports : int#(FROM: 0, TO: 100) a, int#(FROM: 0, TO: 100) b, int#(FROM: 0, TO: 100) c -> int result
     │                                                       ┬                         ┬                         ┬        ───┬──  
     │                                                       ╰──────────────────────────────────────────────────────────────────── 'a' declared here
     │                                                                                 │                         │           │    
     │                                                                                 ╰────────────────────────────────────────── 'b' declared here
     │                                                                                                           │           │    
     │                                                                                                           ╰──────────────── This port is not strongly connected to the strongly connected port cluster 'a', 'b', 'result'.
An input and output port are strongly connected if there is a direct dependency path from the input port to the output port.
Strongly connected ports are also transitive.
If you do not wish to change your design, then 'virtually' connect this port to the strongly connected cluster by explicitly annotating its absolute latency.
     │                                                                                                                       │    
     │                                                                                                                       ╰──── 'result' declared here
─────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
     ╭─[ test.sus:278:107 ]
     │
 278 │     interface disjoint_ports : int#(FROM: 0, TO: 100) a, int#(FROM: 0, TO: 100) b, int#(FROM: 0, TO: 100) c -> int result
     │                                                                                                           ┬  
     │                                                                                                           ╰── Unused Variable: This variable does not affect the output ports of this module
─────╯
Error: No Unique assignment for Port Latency. Options are:
- '2 from x'3
- '1 from y'1
Try specifying an explicit latency or rework the module to remove this ambiguity
     ╭─[ test.sus:284:96 ]
     │
 284 │     interface undeteriminable_input_latency : int#(FROM: 0, TO: 100) a, int#(FROM: 0, TO: 100) b -> int x, int y
     │                                                                                                ┬        ┬      ┬  
     │                                                                                                ╰────────────────── No Unique assignment for Port Latency. Options are:
- '2 from x'3
- '1 from y'1
Try specifying an explicit latency or rework the module to remove this ambiguity
     │                                                                                                         │      │  
     │                                                                                                         ╰───────── 'x' declared here
     │                                                                                                                │  
     │                                                                                                                ╰── 'y' declared here
─────╯
Error: Conflicting specified latency

a'0
-> nio'1 (+1)
-> x'2 (+1)

But this was specified as x'1
     ╭─[ test.sus:325:86 ]
     │
 325 │     interface conflicting_latency_declarations : int#(FROM: 0, TO: 100) a'0 -> int x'1
     │                                                                         ┬            ┬  
     │                                                                         ╰─────────────── 'a' declared here
     │                                                                                      │  
     │                                                                                      ╰── Conflicting specified latency

a'0
-> nio'1 (+1)
-> x'2 (+1)

But this was specified as x'1
─────╯
Error: Some parameters of 'r' were still unknown: int #(FROM: ?, TO: ?)
     ╭─[ test.sus:331:59 ]
     │
 331 │     interface bad_cycle : int#(FROM: 0, TO: 100) a -> int r
     │                                                           ┬  
     │                                                           ╰── Some parameters of 'r' were still unknown: int #(FROM: ?, TO: ?)
─────╯
Error: Some parameters of 'state_reg' were still unknown: int #(FROM: ?, TO: ?)
     ╭─[ test.sus:332:12 ]
     │
 332 │     state int state_reg
     │               ────┬────  
     │                   ╰────── Some parameters of 'state_reg' were still unknown: int #(FROM: ?, TO: ?)
─────╯
Error: This instruction is part of a net-positive latency cycle of +1

state_reg'0
-> state_reg'1 (+1)

Which conflicts with the starting latency
     ╭─[ test.sus:332:12 ]
     │
 332 │     state int state_reg
     │               ────┬────  
     │                   ╰────── This instruction is part of a net-positive latency cycle of +1

state_reg'0
-> state_reg'1 (+1)

Which conflicts with the starting latency
─────╯
Error: Some parameters of '_1' were still unknown: int #(FROM: ?, TO: ?)
     ╭─[ test.sus:335:6 ]
     │
 335 │     r = state_reg
     │         ────┬────  
     │             ╰────── Some parameters of '_1' were still unknown: int #(FROM: ?, TO: ?)
─────╯
Error: Some parameters of '_2' were still unknown: int #(FROM: ?, TO: ?)
     ╭─[ test.sus:337:18 ]
     │
 337 │     reg state_reg = state_reg + a
     │                     ────┬────  
     │                         ╰────── Some parameters of '_2' were still unknown: int #(FROM: ?, TO: ?)
─────╯
Error: Some parameters of '_4' were still unknown: int #(FROM: ?, TO: ?)
     ╭─[ test.sus:337:18 ]
     │
 337 │     reg state_reg = state_reg + a
     │                     ──────┬──────  
     │                           ╰──────── Some parameters of '_4' were still unknown: int #(FROM: ?, TO: ?)
─────╯
Error: This instruction is part of a net-positive latency cycle of +5

test'0
-> _module_taking_time_i'-5 (-5)
-> _module_taking_time_o'0 (+5)
-> test'5 (+5)

Which conflicts with the starting latency
     ╭─[ test.sus:360:29 ]
     │
 360 │     state int#(FROM: 0, TO: 7) test
     │                                ──┬─  
     │                                  ╰─── This instruction is part of a net-positive latency cycle of +5

test'0
-> _module_taking_time_i'-5 (-5)
-> _module_taking_time_o'0 (+5)
-> test'5 (+5)

Which conflicts with the starting latency
─────╯
Error: This instruction is part of a net-positive latency cycle of +5

test'0
-> _module_taking_time_i'-5 (-5)
-> _module_taking_time_o'0 (+5)
-> test'5 (+5)

Which conflicts with the starting latency
     ╭─[ test.sus:363:9 ]
     │
 363 │     test = module_taking_time(test+a)
     │            ─────────┬────────  
     │                     ╰────────── This instruction is part of a net-positive latency cycle of +5

test'0
-> _module_taking_time_i'-5 (-5)
-> _module_taking_time_o'0 (+5)
-> test'5 (+5)

Which conflicts with the starting latency
─────╯
Error: This instruction is part of a net-positive latency cycle of +5

test'0
-> _module_taking_time_i'-5 (-5)
-> _module_taking_time_o'0 (+5)
-> test'5 (+5)

Which conflicts with the starting latency
     ╭─[ test.sus:363:9 ]
     │
 363 │     test = module_taking_time(test+a)
     │            ─────────┬────────  
     │                     ╰────────── This instruction is part of a net-positive latency cycle of +5

test'0
-> _module_taking_time_i'-5 (-5)
-> _module_taking_time_o'0 (+5)
-> test'5 (+5)

Which conflicts with the starting latency
─────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
     ╭─[ test.sus:375:34 ]
     │
 375 │     interface offset_latency : T i'0 -> T o'-5
     │                                  ┬  
     │                                  ╰── Unused Variable: This variable does not affect the output ports of this module
─────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
     ╭─[ test.sus:393:33 ]
     │
 393 │     interface input_only : bool i
     │                                 ┬  
     │                                 ╰── Unused Variable: This variable does not affect the output ports of this module
─────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
     ╭─[ test.sus:394:13 ]
     │
 394 │     state bool loop
     │                ──┬─  
     │                  ╰─── Unused Variable: This variable does not affect the output ports of this module
─────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
     ╭─[ test.sus:400:43 ]
     │
 400 │     interface multiple_inputs_only : bool i'0, bool i2'0
     │                                           ┬  
     │                                           ╰── Unused Variable: This variable does not affect the output ports of this module
─────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
     ╭─[ test.sus:400:53 ]
     │
 400 │     interface multiple_inputs_only : bool i'0, bool i2'0
     │                                                     ─┬  
     │                                                      ╰── Unused Variable: This variable does not affect the output ports of this module
─────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
     ╭─[ test.sus:401:13 ]
     │
 401 │     state bool loop
     │                ──┬─  
     │                  ╰─── Unused Variable: This variable does not affect the output ports of this module
─────╯
Error: 'contains_submodule_submodule' conflicts with other declarations:
     ╭─[ test.sus:441:8 ]
     │
 441 │ module contains_submodule_submodule {
     │        ──────────────┬─────────────  
     │                      ╰─────────────── 'contains_submodule_submodule' conflicts with other declarations:
     │ 
 597 │ module contains_submodule_submodule {
     │        ──────────────┬─────────────  
     │                      ╰─────────────── Conflicts with
─────╯
Warning: Not Instantiating contains_submodule_submodule #() due to abstract typing errors
     ╭─[ test.sus:441:8 ]
     │
 441 │ module contains_submodule_submodule {
     │        ──────────────┬─────────────  
     │                      ╰─────────────── Not Instantiating contains_submodule_submodule #() due to abstract typing errors
─────╯
Error: A function call expects this to be a callable interface, the interface `doNothing` is not callable
     ╭─[ test.sus:445:2 ]
     │
 445 │     doNothing()
     │     ────┬────  
     │         ╰────── A function call expects this to be a callable interface, the interface `doNothing` is not callable
     │
     ├─[ test.sus:445:2 ]
     │
 431 │ module doNothing {}
     │        ────┬────  
     │            ╰────── Field 'doNothing' declared here
─────╯
Warning: Clock 'Unconnected_clock_1' has no driver. Non-input clocks require exactly one driving submodule. Defaulting to 'clk'
     ╭─[ test.sus:462:7 ]
     │
 462 │     bool b = xor(true, false)
     │          ┬  
     │          ╰── Clock 'Unconnected_clock_1' has no driver. Non-input clocks require exactly one driving submodule. Defaulting to 'clk'
─────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
     ╭─[ test.sus:462:7 ]
     │
 462 │     bool b = xor(true, false)
     │          ┬  
     │          ╰── Unused Variable: This variable does not affect the output ports of this module
─────╯
Warning: Not Instantiating use_submodule_named_ports #() due to abstract typing errors
     ╭─[ test.sus:583:8 ]
     │
 583 │ module use_submodule_named_ports {
     │        ────────────┬────────────  
     │                    ╰────────────── Not Instantiating use_submodule_named_ports #() due to abstract typing errors
─────╯
Error: No such field 'port_a' on submodule_named_ports #(). Available fields are 'submodule_named_ports'
     ╭─[ test.sus:590:5 ]
     │
 590 │     sm.port_a = i
     │        ───┬──  
     │           ╰──── No such field 'port_a' on submodule_named_ports #(). Available fields are 'submodule_named_ports'
     │
     ├─[ test.sus:590:5 ]
     │
 576 │ module submodule_named_ports {
     │        ──────────┬──────────  
     │                  ╰──────────── Module 'submodule_named_ports' defined here. module submodule_named_ports #():
domain default:
interface submodule_named_ports:
	input int#(FROM: 0, TO: 100) port_a
	input int#(FROM: 0, TO: 100) port_b
	->
	output int port_c
─────╯
Error: No such field 'port_b' on submodule_named_ports #(). Available fields are 'submodule_named_ports'
     ╭─[ test.sus:592:5 ]
     │
 592 │     sm.port_b = i
     │        ───┬──  
     │           ╰──── No such field 'port_b' on submodule_named_ports #(). Available fields are 'submodule_named_ports'
     │
     ├─[ test.sus:592:5 ]
     │
 576 │ module submodule_named_ports {
     │        ──────────┬──────────  
     │                  ╰──────────── Module 'submodule_named_ports' defined here. module submodule_named_ports #():
domain default:
interface submodule_named_ports:
	input int#(FROM: 0, TO: 100) port_a
	input int#(FROM: 0, TO: 100) port_b
	->
	output int port_c
─────╯
Error: No such field 'port_c' on submodule_named_ports #(). Available fields are 'submodule_named_ports'
     ╭─[ test.sus:594:9 ]
     │
 594 │     o = sm.port_c
     │            ───┬──  
     │               ╰──── No such field 'port_c' on submodule_named_ports #(). Available fields are 'submodule_named_ports'
     │
     ├─[ test.sus:594:9 ]
     │
 576 │ module submodule_named_ports {
     │        ──────────┬──────────  
     │                  ╰──────────── Module 'submodule_named_ports' defined here. module submodule_named_ports #():
domain default:
interface submodule_named_ports:
	input int#(FROM: 0, TO: 100) port_a
	input int#(FROM: 0, TO: 100) port_b
	->
	output int port_c
─────╯
Error: 'contains_submodule_submodule' conflicts with other declarations:
     ╭─[ test.sus:597:8 ]
     │
 597 │ module contains_submodule_submodule {
     │        ──────────────┬─────────────  
     │                      ╰─────────────── 'contains_submodule_submodule' conflicts with other declarations:
     │
     ├─[ test.sus:597:8 ]
     │
 441 │ module contains_submodule_submodule {
     │        ──────────────┬─────────────  
     │                      ╰─────────────── Conflicts with
─────╯
Warning: Not Instantiating contains_submodule_submodule #() due to abstract typing errors
     ╭─[ test.sus:597:8 ]
     │
 597 │ module contains_submodule_submodule {
     │        ──────────────┬─────────────  
     │                      ╰─────────────── Not Instantiating contains_submodule_submodule #() due to abstract typing errors
─────╯
Error: A function call expects this to be a callable interface, the interface `doNothing` is not callable
     ╭─[ test.sus:601:2 ]
     │
 601 │     doNothing()
     │     ────┬────  
     │         ╰────── A function call expects this to be a callable interface, the interface `doNothing` is not callable
     │
     ├─[ test.sus:601:2 ]
     │
 431 │ module doNothing {}
     │        ────┬────  
     │            ╰────── Field 'doNothing' declared here
─────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
     ╭─[ test.sus:608:22 ]
     │
 608 │     interface in : bool i'0
     │                         ┬  
     │                         ╰── Unused Variable: This variable does not affect the output ports of this module
─────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
     ╭─[ test.sus:613:40 ]
     │
 613 │     interface in : int#(FROM: 0, TO: 100) i'0
     │                                           ┬  
     │                                           ╰── Unused Variable: This variable does not affect the output ports of this module
─────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
     ╭─[ test.sus:619:31 ]
     │
 619 │     interface in : bool[20][512] i'0
     │                                  ┬  
     │                                  ╰── Unused Variable: This variable does not affect the output ports of this module
─────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
     ╭─[ test.sus:625:39 ]
     │
 625 │     interface offset_backwards : bool i'0 -> bool o'-5
     │                                       ┬  
     │                                       ╰── Unused Variable: This variable does not affect the output ports of this module
─────╯
Warning: Not Instantiating dual_port_mem #() due to abstract typing errors
     ╭─[ test.sus:629:8 ]
     │
 629 │ module dual_port_mem {
     │        ──────┬──────  
     │              ╰──────── Not Instantiating dual_port_mem #() due to abstract typing errors
─────╯
Error: Duplicate interface 'write' declaration
     ╭─[ test.sus:632:12 ]
     │
 632 │     interface write : bool write, bool[20] wr_data, int#(FROM:0, TO: 511) wr_addr
     │               ──┬──        ──┬──  
     │                 ╰───────────────── Duplicate interface 'write' declaration
     │                              │    
     │                              ╰──── port 'write' declared here
─────╯
Error: This declaration conflicts with a previous declaration in the same scope, found interface 'write'
     ╭─[ test.sus:632:25 ]
     │
 632 │     interface write : bool write, bool[20] wr_data, int#(FROM:0, TO: 511) wr_addr
     │               ──┬──        ──┬──  
     │                 ╰───────────────── 'write' declared here
     │                              │    
     │                              ╰──── This declaration conflicts with a previous declaration in the same scope, found interface 'write'
─────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
     ╭─[ test.sus:632:25 ]
     │
 632 │     interface write : bool write, bool[20] wr_data, int#(FROM:0, TO: 511) wr_addr
     │                            ──┬──  
     │                              ╰──── Unused Variable: This variable does not affect the output ports of this module
─────╯
Error: Duplicate interface 'read' declaration
     ╭─[ test.sus:634:12 ]
     │
 634 │     interface read : bool read, int#(FROM:0, TO: 511) rd_addr -> bool[20] rd_data
     │               ──┬─        ──┬─  
     │                 ╰─────────────── Duplicate interface 'read' declaration
     │                             │   
     │                             ╰─── port 'read' declared here
─────╯
Error: This declaration conflicts with a previous declaration in the same scope, found interface 'read'
     ╭─[ test.sus:634:24 ]
     │
 634 │     interface read : bool read, int#(FROM:0, TO: 511) rd_addr -> bool[20] rd_data
     │               ──┬─        ──┬─  
     │                 ╰─────────────── 'read' declared here
     │                             │   
     │                             ╰─── This declaration conflicts with a previous declaration in the same scope, found interface 'read'
─────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
     ╭─[ test.sus:634:24 ]
     │
 634 │     interface read : bool read, int#(FROM:0, TO: 511) rd_addr -> bool[20] rd_data
     │                           ──┬─  
     │                             ╰─── Unused Variable: This variable does not affect the output ports of this module
─────╯
Error: Can only use conditional bindings on triggers. 'write' is an interface
     ╭─[ test.sus:636:7 ]
     │
 636 │     when write {
     │          ──┬──  
     │            ╰──── Can only use conditional bindings on triggers. 'write' is an interface
     │
     ├─[ test.sus:636:7 ]
     │
 632 │     interface write : bool write, bool[20] wr_data, int#(FROM:0, TO: 511) wr_addr
     │               ──┬──  
     │                 ╰──── Interface 'write' defined here
─────╯
Error: Too few bindings. This interface provides 3 read-only bindings, but 0 were provided.
     ╭─[ test.sus:636:7 ]
     │
 636 │     when write {
     │          ──┬──  
     │            ╰──── Too few bindings. This interface provides 3 read-only bindings, but 0 were provided.
     │
     ├─[ test.sus:636:7 ]
     │
 632 │     interface write : bool write, bool[20] wr_data, int#(FROM:0, TO: 511) wr_addr
     │               ──┬──  
     │                 ╰──── Interface 'write' defined here
─────╯
Error: No such field 'i' on cross_memory #(). Available fields are 'cross_memory', 'in', 'out'
     ╭─[ test.sus:641:7 ]
     │
 641 │     cr_m.i = mem
     │          ┬  
     │          ╰── No such field 'i' on cross_memory #(). Available fields are 'cross_memory', 'in', 'out'
     │
     ├─[ test.sus:641:7 ]
     │
 618 │ module cross_memory {
     │        ──────┬─────  
     │              ╰─────── Module 'cross_memory' defined here. module cross_memory #():
domain default:
interface in:
	input bool[20][512] i'0
interface out:
	->
	output bool[20][512] o'0
─────╯
Error: Can only use conditional bindings on triggers. 'read' is an interface
     ╭─[ test.sus:642:7 ]
     │
 642 │     when read {
     │          ──┬─  
     │            ╰─── Can only use conditional bindings on triggers. 'read' is an interface
     │
     ├─[ test.sus:642:7 ]
     │
 634 │     interface read : bool read, int#(FROM:0, TO: 511) rd_addr -> bool[20] rd_data
     │               ──┬─  
     │                 ╰─── Interface 'read' defined here
─────╯
Error: Too few bindings. This interface provides 1 writable bindings, but 0 were provided.
     ╭─[ test.sus:642:7 ]
     │
 642 │     when read {
     │          ──┬─  
     │            ╰─── Too few bindings. This interface provides 1 writable bindings, but 0 were provided.
     │
     ├─[ test.sus:642:7 ]
     │
 634 │     interface read : bool read, int#(FROM:0, TO: 511) rd_addr -> bool[20] rd_data
     │               ──┬─  
     │                 ╰─── Interface 'read' defined here
─────╯
Error: Too few bindings. This interface provides 2 read-only bindings, but 0 were provided.
     ╭─[ test.sus:642:7 ]
     │
 642 │     when read {
     │          ──┬─  
     │            ╰─── Too few bindings. This interface provides 2 read-only bindings, but 0 were provided.
     │
     ├─[ test.sus:642:7 ]
     │
 634 │     interface read : bool read, int#(FROM:0, TO: 511) rd_addr -> bool[20] rd_data
     │               ──┬─  
     │                 ╰─── Interface 'read' defined here
─────╯
Error: No such field 'o' on cross_memory #(). Available fields are 'cross_memory', 'in', 'out'
     ╭─[ test.sus:643:18 ]
     │
 643 │        rd_data = cr_m.o[rd_addr]
     │                       ┬  
     │                       ╰── No such field 'o' on cross_memory #(). Available fields are 'cross_memory', 'in', 'out'
     │
     ├─[ test.sus:643:18 ]
     │
 618 │ module cross_memory {
     │        ──────┬─────  
     │              ╰─────── Module 'cross_memory' defined here. module cross_memory #():
domain default:
interface in:
	input bool[20][512] i'0
interface out:
	->
	output bool[20][512] o'0
─────╯
Warning: Not Instantiating use_fifo #() due to abstract typing errors
     ╭─[ test.sus:647:8 ]
     │
 647 │ module use_fifo {
     │        ────┬───  
     │            ╰───── Not Instantiating use_fifo #() due to abstract typing errors
─────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
     ╭─[ test.sus:651:11 ]
     │
 651 │     bool[20] data
     │              ──┬─  
     │                ╰─── Unused Variable: This variable does not affect the output ports of this module
─────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
     ╭─[ test.sus:653:7 ]
     │
 653 │     bool valid, bool[20] data2 = fiii.pop(true)
     │          ──┬──  
     │            ╰──── Unused Variable: This variable does not affect the output ports of this module
─────╯
Error: Excess output targets. Function returns 1 results, but 2 targets were given.
     ╭─[ test.sus:653:14 ]
     │
 653 │     bool valid, bool[20] data2 = fiii.pop(true)
     │                 ───────┬──────  
     │                        ╰──────── Excess output targets. Function returns 1 results, but 2 targets were given.
     │
     ├─[ memory.sus:150:12 ]
     │
 150 │     action pop'0 : -> T pop_data'1 {
     │            ─┬─  
     │             ╰─── Interface 'pop' defined here
─────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
     ╭─[ test.sus:653:23 ]
     │
 653 │     bool valid, bool[20] data2 = fiii.pop(true)
     │                          ──┬──  
     │                            ╰──── Unused Variable: This variable does not affect the output ports of this module
─────╯
Error: Excess argument. Function takes 0 args, but 1 were passed.
     ╭─[ test.sus:653:40 ]
     │
 653 │     bool valid, bool[20] data2 = fiii.pop(true)
     │                                           ──┬─  
     │                                             ╰─── Excess argument. Function takes 0 args, but 1 were passed.
     │
     ├─[ memory.sus:150:12 ]
     │
 150 │     action pop'0 : -> T pop_data'1 {
     │            ─┬─  
     │             ╰─── Interface 'pop' defined here
─────╯
Warning: Not Instantiating test_separated_domain #() due to abstract typing errors
     ╭─[ test.sus:658:8 ]
     │
 658 │ module test_separated_domain {
     │        ──────────┬──────────  
     │                  ╰──────────── Not Instantiating test_separated_domain #() due to abstract typing errors
─────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
     ╭─[ test.sus:659:44 ]
     │
 659 │     interface test_separated_domain : bool main
     │                                            ──┬─  
     │                                              ╰─── Unused Variable: This variable does not affect the output ports of this module
─────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
     ╭─[ test.sus:660:7 ]
     │
 660 │     bool domain2
     │          ───┬───  
     │             ╰───── Unused Variable: This variable does not affect the output ports of this module
─────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
     ╭─[ test.sus:662:7 ]
     │
 662 │     bool domain3
     │          ───┬───  
     │             ╰───── Unused Variable: This variable does not affect the output ports of this module
─────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
     ╭─[ test.sus:664:7 ]
     │
 664 │     bool domain4
     │          ───┬───  
     │             ╰───── Unused Variable: This variable does not affect the output ports of this module
─────╯
Error: No such field 'i' on cross_bool #(). Available fields are 'cross_bool', 'in', 'out'
     ╭─[ test.sus:667:5 ]
     │
 667 │     ci.i = domain3
     │        ┬  
     │        ╰── No such field 'i' on cross_bool #(). Available fields are 'cross_bool', 'in', 'out'
     │
     ├─[ test.sus:667:5 ]
     │
 607 │ module cross_bool {
     │        ─────┬────  
     │             ╰────── Module 'cross_bool' defined here. module cross_bool #():
domain default:
interface in:
	input bool i'0
interface out:
	->
	output bool o'0
─────╯
Error: No such field 'o' on cross_bool #(). Available fields are 'cross_bool', 'in', 'out'
     ╭─[ test.sus:668:15 ]
     │
 668 │     domain4 = ci.o
     │                  ┬  
     │                  ╰── No such field 'o' on cross_bool #(). Available fields are 'cross_bool', 'in', 'out'
     │
     ├─[ test.sus:668:15 ]
     │
 607 │ module cross_bool {
     │        ─────┬────  
     │             ╰────── Module 'cross_bool' defined here. module cross_bool #():
domain default:
interface in:
	input bool i'0
interface out:
	->
	output bool o'0
─────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
     ╭─[ test.sus:670:7 ]
     │
 670 │     bool domain5
     │          ───┬───  
     │             ╰───── Unused Variable: This variable does not affect the output ports of this module
─────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
     ╭─[ test.sus:672:26 ]
     │
 672 │     int #(FROM: 0, TO: 199) my_int
     │                             ───┬──  
     │                                ╰──── Unused Variable: This variable does not affect the output ports of this module
─────╯
Warning: Not Instantiating use_no_input_module #() due to abstract typing errors
     ╭─[ test.sus:677:8 ]
     │
 677 │ module use_no_input_module {
     │        ─────────┬─────────  
     │                 ╰─────────── Not Instantiating use_no_input_module #() due to abstract typing errors
─────╯
Error: A function call expects this to be a callable interface, the interface `no_port_module` is not callable
     ╭─[ test.sus:678:2 ]
     │
 678 │     no_port_module()
     │     ───────┬──────  
     │            ╰──────── A function call expects this to be a callable interface, the interface `no_port_module` is not callable
     │
     ├─[ test.sus:678:2 ]
     │
 675 │ module no_port_module {}
     │        ───────┬──────  
     │               ╰──────── Field 'no_port_module' declared here
─────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
     ╭─[ test.sus:681:6 ]
     │
 681 │     int x = no_port()
     │         ┬  
     │         ╰── Unused Variable: This variable does not affect the output ports of this module
─────╯
Error: A function call expects this to be a callable interface, the interface `no_port_module` is not callable
     ╭─[ test.sus:681:10 ]
     │
 681 │     int x = no_port()
     │             ───┬───  
     │                ╰───── A function call expects this to be a callable interface, the interface `no_port_module` is not callable
     │
     ├─[ test.sus:681:10 ]
     │
 675 │ module no_port_module {}
     │        ───────┬──────  
     │               ╰──────── Field 'no_port_module' declared here
─────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
     ╭─[ test.sus:686:40 ]
     │
 686 │        interface v : int#(FROM: 0, TO: 100) a -> int b
     │                                             ┬  
     │                                             ╰── Unused Variable: This variable does not affect the output ports of this module
─────╯
Warning: Not Instantiating test_write_to_gen_var #() due to abstract typing errors
     ╭─[ test.sus:690:8 ]
     │
 690 │ module test_write_to_gen_var {
     │        ──────────┬──────────  
     │                  ╰──────────── Not Instantiating test_write_to_gen_var #() due to abstract typing errors
─────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
     ╭─[ test.sus:691:6 ]
     │
 691 │     int a
     │         ┬  
     │         ╰── Unused Variable: This variable does not affect the output ports of this module
─────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
     ╭─[ test.sus:693:10 ]
     │
 693 │     gen int b
     │             ┬  
     │             ╰── Unused Variable: This variable does not affect the output ports of this module
─────╯
Error: Attempting to write a runtime value to a generative target
     ╭─[ test.sus:701:6 ]
     │
 701 │     b = a
     │     ┬   ┬  
     │     ╰────── This is a generative target
     │         │  
     │         ╰── Attempting to write a runtime value to a generative target
─────╯
Warning: Not Instantiating use_bad_interface #() due to abstract typing errors
     ╭─[ test.sus:704:8 ]
     │
 704 │ module use_bad_interface {
     │        ────────┬────────  
     │                ╰────────── Not Instantiating use_bad_interface #() due to abstract typing errors
─────╯
Warning: The result of this expression is not used. Only function calls can return nothing. 
     ╭─[ test.sus:707:2 ]
     │
 707 │     mm.a
     │     ──┬─  
     │       ╰─── The result of this expression is not used. Only function calls can return nothing. 
─────╯
Error: No such field 'a' on mod_with_unused_interface #(). Available fields are 'mod_with_unused_interface', 'v'
     ╭─[ test.sus:707:5 ]
     │
 707 │     mm.a
     │        ┬  
     │        ╰── No such field 'a' on mod_with_unused_interface #(). Available fields are 'mod_with_unused_interface', 'v'
     │
     ├─[ test.sus:707:5 ]
     │
 684 │ module mod_with_unused_interface {
     │        ────────────┬────────────  
     │                    ╰────────────── Module 'mod_with_unused_interface' defined here. module mod_with_unused_interface #():
domain default:
interface v:
	input int#(FROM: 0, TO: 100) a
	->
	output int b
─────╯
Warning: Not Instantiating sequenceDownFrom #() due to abstract typing errors
     ╭─[ test.sus:720:8 ]
     │
 720 │ module sequenceDownFrom {
     │        ────────┬───────  
     │                ╰───────── Not Instantiating sequenceDownFrom #() due to abstract typing errors
─────╯
Error: Duplicate interface 'start' declaration
     ╭─[ test.sus:723:12 ]
     │
 723 │     interface start : bool start'0, int#(FROM: 0, TO: 100) upTo'0
     │               ──┬──        ──┬──  
     │                 ╰───────────────── Duplicate interface 'start' declaration
     │                              │    
     │                              ╰──── port 'start' declared here
─────╯
Error: This declaration conflicts with a previous declaration in the same scope, found interface 'start'
     ╭─[ test.sus:723:25 ]
     │
 723 │     interface start : bool start'0, int#(FROM: 0, TO: 100) upTo'0
     │               ──┬──        ──┬──  
     │                 ╰───────────────── 'start' declared here
     │                              │    
     │                              ╰──── This declaration conflicts with a previous declaration in the same scope, found interface 'start'
─────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
     ╭─[ test.sus:723:25 ]
     │
 723 │     interface start : bool start'0, int#(FROM: 0, TO: 100) upTo'0
     │                            ──┬──  
     │                              ╰──── Unused Variable: This variable does not affect the output ports of this module
─────╯
Error: Can't write to an interface. Use a function call or interface connector instead
     ╭─[ test.sus:730:2 ]
     │
 730 │     start_cr.i = start
     │     ─────┬────  
     │          ╰────── Can't write to an interface. Use a function call or interface connector instead
─────╯
Error: No such field 'i' on cross_bool #(). Available fields are 'cross_bool', 'in', 'out'
     ╭─[ test.sus:730:11 ]
     │
 730 │     start_cr.i = start
     │              ┬  
     │              ╰── No such field 'i' on cross_bool #(). Available fields are 'cross_bool', 'in', 'out'
     │
     ├─[ test.sus:730:11 ]
     │
 607 │ module cross_bool {
     │        ─────┬────  
     │             ╰────── Module 'cross_bool' defined here. module cross_bool #():
domain default:
interface in:
	input bool i'0
interface out:
	->
	output bool o'0
─────╯
Error: No such field 'i' on cross_int #(). Available fields are 'cross_int', 'in', 'out'
     ╭─[ test.sus:733:10 ]
     │
 733 │     upTo_cr.i = upTo
     │             ┬  
     │             ╰── No such field 'i' on cross_int #(). Available fields are 'cross_int', 'in', 'out'
     │
     ├─[ test.sus:733:10 ]
     │
 612 │ module cross_int {
     │        ────┬────  
     │            ╰────── Module 'cross_int' defined here. module cross_int #():
domain default:
interface in:
	input int#(FROM: 0, TO: 100) i'0
interface out:
	->
	output int o'0
─────╯
Error: No such field 'o' on cross_bool #(). Available fields are 'cross_bool', 'in', 'out'
     ╭─[ test.sus:736:19 ]
     │
 736 │     ready = ready_cr.o
     │                      ┬  
     │                      ╰── No such field 'o' on cross_bool #(). Available fields are 'cross_bool', 'in', 'out'
     │
     ├─[ test.sus:736:19 ]
     │
 607 │ module cross_bool {
     │        ─────┬────  
     │             ╰────── Module 'cross_bool' defined here. module cross_bool #():
domain default:
interface in:
	input bool i'0
interface out:
	->
	output bool o'0
─────╯
Error: No such field 'i' on cross_bool #(). Available fields are 'cross_bool', 'in', 'out'
     ╭─[ test.sus:739:11 ]
     │
 739 │     ready_cr.i = !valid
     │              ┬  
     │              ╰── No such field 'i' on cross_bool #(). Available fields are 'cross_bool', 'in', 'out'
     │
     ├─[ test.sus:739:11 ]
     │
 607 │ module cross_bool {
     │        ─────┬────  
     │             ╰────── Module 'cross_bool' defined here. module cross_bool #():
domain default:
interface in:
	input bool i'0
interface out:
	->
	output bool o'0
─────╯
Error: No such field 'o' on cross_bool #(). Available fields are 'cross_bool', 'in', 'out'
     ╭─[ test.sus:744:16 ]
     │
 744 │     when start_cr.o {
     │                   ┬  
     │                   ╰── No such field 'o' on cross_bool #(). Available fields are 'cross_bool', 'in', 'out'
     │
     ├─[ test.sus:744:16 ]
     │
 607 │ module cross_bool {
     │        ─────┬────  
     │             ╰────── Module 'cross_bool' defined here. module cross_bool #():
domain default:
interface in:
	input bool i'0
interface out:
	->
	output bool o'0
─────╯
Error: No such field 'o' on cross_int #(). Available fields are 'cross_int', 'in', 'out'
     ╭─[ test.sus:745:19 ]
     │
 745 │        index = upTo_cr.o
     │                        ┬  
     │                        ╰── No such field 'o' on cross_int #(). Available fields are 'cross_int', 'in', 'out'
     │
     ├─[ test.sus:745:19 ]
     │
 612 │ module cross_int {
     │        ────┬────  
     │            ╰────── Module 'cross_int' defined here. module cross_int #():
domain default:
interface in:
	input int#(FROM: 0, TO: 100) i'0
interface out:
	->
	output int o'0
─────╯
Warning: Not Instantiating sumUpTo #() due to abstract typing errors of submodules:
- sequenceDownFrom

     ╭─[ test.sus:749:8 ]
     │
 749 │ module sumUpTo {
     │        ───┬───  
     │           ╰───── Not Instantiating sumUpTo #() due to abstract typing errors of submodules:
- sequenceDownFrom

─────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
     ╭─[ test.sus:750:30 ]
     │
 750 │     interface sumUpTo : bool start
     │                              ──┬──  
     │                                ╰──── Unused Variable: This variable does not affect the output ports of this module
─────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
     ╭─[ test.sus:756:7 ]
     │
 756 │     bool re = sdf.ready
     │          ─┬  
     │           ╰── Unused Variable: This variable does not affect the output ports of this module
─────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
     ╭─[ test.sus:758:7 ]
     │
 758 │     bool iter_valid, int iter_index = sdf.iter()
     │          ─────┬────  
     │               ╰────── Unused Variable: This variable does not affect the output ports of this module
─────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
     ╭─[ test.sus:758:23 ]
     │
 758 │     bool iter_valid, int iter_index = sdf.iter()
     │                          ─────┬────  
     │                               ╰────── Unused Variable: This variable does not affect the output ports of this module
─────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
     ╭─[ test.sus:760:7 ]
     │
 760 │        int idx = iter_index
     │            ─┬─  
     │             ╰─── Unused Variable: This variable does not affect the output ports of this module
─────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
     ╭─[ test.sus:763:6 ]
     │
 763 │     int beep
     │         ──┬─  
     │           ╰─── Unused Variable: This variable does not affect the output ports of this module
─────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
     ╭─[ test.sus:766:22 ]
     │
 766 │ module test #(T, int MY_INPUT) {
     │                      ────┬───  
     │                          ╰───── Unused Variable: This variable does not affect the output ports of this module
─────╯
Error: int has no template argument named 'beep'
     ╭─[ test.sus:767:30 ]
     │
 767 │     interface test : ::int #(beep: 20 > 3, BEEP: int) ab
     │                              ──┬─  
     │                                ╰─── int has no template argument named 'beep'
     │
     ├─[ core.sus:13:20 ]
     │
  13 │ __builtin__ struct int #(int FROM, int TO) {}
     │                    ─┬─  
     │                     ╰─── 'int' defined here
─────╯
Error: int has no template argument named 'BEEP'
     ╭─[ test.sus:767:44 ]
     │
 767 │     interface test : ::int #(beep: 20 > 3, BEEP: int) ab
     │                                            ──┬─  
     │                                              ╰─── int has no template argument named 'BEEP'
     │
     ├─[ core.sus:13:20 ]
     │
  13 │ __builtin__ struct int #(int FROM, int TO) {}
     │                    ─┬─  
     │                     ╰─── 'int' defined here
─────╯
Error: int is not a named wire: local or constant, it is a Struct instead!
     ╭─[ test.sus:767:50 ]
     │
 767 │     interface test : ::int #(beep: 20 > 3, BEEP: int) ab
     │                                                  ─┬─  
     │                                                   ╰─── int is not a named wire: local or constant, it is a Struct instead!
     │
     ├─[ core.sus:13:20 ]
     │
  13 │ __builtin__ struct int #(int FROM, int TO) {}
     │                    ─┬─  
     │                     ╰─── 'int' defined here
─────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
     ╭─[ test.sus:767:55 ]
     │
 767 │     interface test : ::int #(beep: 20 > 3, BEEP: int) ab
     │                                                       ─┬  
     │                                                        ╰── Unused Variable: This variable does not affect the output ports of this module
─────╯
Error: 'MY_INPUT' is read-only
     ╭─[ test.sus:769:2 ]
     │
 769 │     MY_INPUT = 3
     │     ────┬───  
     │         ╰───── 'MY_INPUT' is read-only
     │
     ├─[ test.sus:769:2 ]
     │
 766 │ module test #(T, int MY_INPUT) {
     │                      ────┬───  
     │                          ╰───── 'MY_INPUT' declared here
─────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
     ╭─[ test.sus:771:12 ]
     │
 771 │     input int beep
     │               ──┬─  
     │                 ╰─── Unused Variable: This variable does not affect the output ports of this module
─────╯
Error: 'beep' is read-only
     ╭─[ test.sus:773:2 ]
     │
 773 │     beep = 3
     │     ──┬─  
     │       ╰─── 'beep' is read-only
     │
     ├─[ test.sus:773:2 ]
     │
 771 │     input int beep
     │               ──┬─  
     │                 ╰─── 'beep' declared here
─────╯
Error: FIFO has no template argument named 'BITWIDTH'
     ╭─[ test.sus:775:9 ]
     │
 775 │     FIFO #(BITWIDTH: 4) badoop
     │            ────┬───  
     │                ╰───── FIFO has no template argument named 'BITWIDTH'
     │
     ├─[ memory.sus:131:8 ]
     │
 131 │ module FIFO #(T, int DEPTH, int MAY_PUSH_LATENCY) {
     │        ──┬─  
     │          ╰─── 'FIFO' defined here
─────╯
Warning: Not Instantiating use_test #() due to abstract typing errors
     ╭─[ test.sus:778:8 ]
     │
 778 │ module use_test {
     │        ────┬───  
     │            ╰───── Not Instantiating use_test #() due to abstract typing errors
─────╯
Error: Could not fully figure out the type of parameter T. '?[...]'
     ╭─[ test.sus:779:2 ]
     │
 779 │     test #(MY_INPUT: 3) test_mod
     │     ─────────┬─────────  
     │              ╰─────────── Could not fully figure out the type of parameter T. '?[...]'
─────╯
Warning: Clock 'Unconnected_clock_1' has no driver. Non-input clocks require exactly one driving submodule. Defaulting to 'clk'
     ╭─[ test.sus:791:25 ]
     │
 791 │     tinyTestMod #(beep: 3) a
     │                            ┬  
     │                            ╰── Clock 'Unconnected_clock_1' has no driver. Non-input clocks require exactly one driving submodule. Defaulting to 'clk'
─────╯
Warning: Unused port 'o'
     ╭─[ test.sus:791:25 ]
     │
 791 │     tinyTestMod #(beep: 3) a
     │                            ┬  
     │                            ╰── Unused port 'o'
     │
     ├─[ test.sus:791:25 ]
     │
 786 │     output int o = beep
     │                ┬  
     │                ╰── Port 'o' declared here
     │ 
 791 │     tinyTestMod #(beep: 3) a
     │                            ┬  
     │                            ╰── a declared here
─────╯
Warning: Clock 'Unconnected_clock_2' has no driver. Non-input clocks require exactly one driving submodule. Defaulting to 'clk'
     ╭─[ test.sus:792:25 ]
     │
 792 │     tinyTestMod #(beep: 4) b
     │                            ┬  
     │                            ╰── Clock 'Unconnected_clock_2' has no driver. Non-input clocks require exactly one driving submodule. Defaulting to 'clk'
─────╯
Warning: Unused port 'o'
     ╭─[ test.sus:792:25 ]
     │
 792 │     tinyTestMod #(beep: 4) b
     │                            ┬  
     │                            ╰── Unused port 'o'
     │
     ├─[ test.sus:792:25 ]
     │
 786 │     output int o = beep
     │                ┬  
     │                ╰── Port 'o' declared here
     │ 
 792 │     tinyTestMod #(beep: 4) b
     │                            ┬  
     │                            ╰── b declared here
─────╯
Warning: Clock 'Unconnected_clock_3' has no driver. Non-input clocks require exactly one driving submodule. Defaulting to 'clk'
     ╭─[ test.sus:793:25 ]
     │
 793 │     tinyTestMod #(beep: 3) c
     │                            ┬  
     │                            ╰── Clock 'Unconnected_clock_3' has no driver. Non-input clocks require exactly one driving submodule. Defaulting to 'clk'
─────╯
Warning: Unused port 'o'
     ╭─[ test.sus:793:25 ]
     │
 793 │     tinyTestMod #(beep: 3) c
     │                            ┬  
     │                            ╰── Unused port 'o'
     │
     ├─[ test.sus:793:25 ]
     │
 786 │     output int o = beep
     │                ┬  
     │                ╰── Port 'o' declared here
     │ 
 793 │     tinyTestMod #(beep: 3) c
     │                            ┬  
     │                            ╰── c declared here
─────╯
Error: Some parameters of 'values' were still unknown: int #(FROM: ?, TO: ?)[1]
     ╭─[ test.sus:799:19 ]
     │
 799 │     input int[WIDTH] values
     │                      ───┬──  
     │                         ╰──── Some parameters of 'values' were still unknown: int #(FROM: ?, TO: ?)[1]
─────╯
Error: Some parameters of 'sum' were still unknown: int #(FROM: ?, TO: ?)
     ╭─[ test.sus:800:13 ]
     │
 800 │     output int sum
     │                ─┬─  
     │                 ╰─── Some parameters of 'sum' were still unknown: int #(FROM: ?, TO: ?)
─────╯
Error: Some parameters of '_1' were still unknown: int #(FROM: ?, TO: ?)
     ╭─[ test.sus:803:9 ]
     │
 803 │        sum = values[0]
     │              ────┬────  
     │                  ╰────── Some parameters of '_1' were still unknown: int #(FROM: ?, TO: ?)
─────╯
Warning: Clock 'Unconnected_clock_1' has no driver. Non-input clocks require exactly one driving submodule. Defaulting to 'clk'
     ╭─[ test.sus:851:46 ]
     │
 851 │     replicate #(NUM_REPLS: 20, T: type int[30]) b
     │                                                 ┬  
     │                                                 ╰── Clock 'Unconnected_clock_1' has no driver. Non-input clocks require exactly one driving submodule. Defaulting to 'clk'
─────╯
Error: Some submodule parameters of b were still unknown: replicate #(T: type int #(FROM: ?, TO: ?)[30], NUM_REPLS: 20)
T can be inferred from:
{*} <: T in T data
{*} = T in T[] result
NUM_REPLS can be inferred if at least one of the following constraint resolves:
    NUM_REPLS == {*} in T[{*}] result

     ╭─[ test.sus:851:46 ]
     │
 851 │     replicate #(NUM_REPLS: 20, T: type int[30]) b
     │                                                 ┬  
     │                                                 ╰── Some submodule parameters of b were still unknown: replicate #(T: type int #(FROM: ?, TO: ?)[30], NUM_REPLS: 20)
T can be inferred from:
{*} <: T in T data
{*} = T in T[] result
NUM_REPLS can be inferred if at least one of the following constraint resolves:
    NUM_REPLS == {*} in T[{*}] result

─────╯
Warning: Clock 'Unconnected_clock_2' has no driver. Non-input clocks require exactly one driving submodule. Defaulting to 'clk'
     ╭─[ test.sus:854:6 ]
     │
 854 │     int val = 3
     │         ─┬─  
     │          ╰─── Clock 'Unconnected_clock_2' has no driver. Non-input clocks require exactly one driving submodule. Defaulting to 'clk'
─────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
     ╭─[ test.sus:854:6 ]
     │
 854 │     int val = 3
     │         ─┬─  
     │          ╰─── Unused Variable: This variable does not affect the output ports of this module
─────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
     ╭─[ test.sus:857:10 ]
     │
 857 │     int[30] out = c.result
     │             ─┬─  
     │              ╰─── Unused Variable: This variable does not affect the output ports of this module
─────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
     ╭─[ test.sus:869:13 ]
     │
 869 │     gen int[8] SOURCES = [3, 2, 4, 5, 1, 2, 7, 6]
     │                ───┬───  
     │                   ╰───── Unused Variable: This variable does not affect the output ports of this module
─────╯
Warning: Clock 'Unconnected_clock_1' has no driver. Non-input clocks require exactly one driving submodule. Defaulting to 'clk'
     ╭─[ test.sus:871:9 ]
     │
 871 │     int[2] inArr
     │            ──┬──  
     │              ╰──── Clock 'Unconnected_clock_1' has no driver. Non-input clocks require exactly one driving submodule. Defaulting to 'clk'
─────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
     ╭─[ test.sus:871:9 ]
     │
 871 │     int[2] inArr
     │            ──┬──  
     │              ╰──── Unused Variable: This variable does not affect the output ports of this module
─────╯
Warning: Clock 'Unconnected_clock_2' has no driver. Non-input clocks require exactly one driving submodule. Defaulting to 'clk'
     ╭─[ test.sus:878:9 ]
     │
 878 │     int[8] beep = permut.permute(SOURCES)
     │            ──┬─  
     │              ╰─── Clock 'Unconnected_clock_2' has no driver. Non-input clocks require exactly one driving submodule. Defaulting to 'clk'
─────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
     ╭─[ test.sus:878:9 ]
     │
 878 │     int[8] beep = permut.permute(SOURCES)
     │            ──┬─  
     │              ╰─── Unused Variable: This variable does not affect the output ports of this module
─────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
     ╭─[ test.sus:882:28 ]
     │
 882 │     interface from : bool[32] instr
     │                               ──┬──  
     │                                 ╰──── Unused Variable: This variable does not affect the output ports of this module
─────╯
Warning: Not Instantiating run_instruction #() due to abstract typing errors
     ╭─[ test.sus:889:8 ]
     │
 889 │ module run_instruction {
     │        ───────┬───────  
     │               ╰───────── Not Instantiating run_instruction #() due to abstract typing errors
─────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
     ╭─[ test.sus:890:42 ]
     │
 890 │     interface run_instruction : bool[32] instr
     │                                          ──┬──  
     │                                            ╰──── Unused Variable: This variable does not affect the output ports of this module
─────╯
Error: Excess output targets. Function returns 0 results, but 1 targets were given.
     ╭─[ test.sus:894:7 ]
     │
 894 │     when decoder.is_jump() : int target_addr {
     │          ────────┬────────  
     │                  ╰────────── Excess output targets. Function returns 0 results, but 1 targets were given.
     │
     ├─[ test.sus:894:7 ]
     │
 883 │     interface is_jump
     │               ───┬───  
     │                  ╰───── Interface 'is_jump' defined here
─────╯
Error: Cannot use conditional bingings because the condition isn't an action or a trigger
     ╭─[ test.sus:894:25 ]
     │
 894 │     when decoder.is_jump() : int target_addr {
     │                            ────────┬────────  
     │                                    ╰────────── Cannot use conditional bingings because the condition isn't an action or a trigger
─────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
     ╭─[ test.sus:894:31 ]
     │
 894 │     when decoder.is_jump() : int target_addr {
     │                                  ─────┬─────  
     │                                       ╰─────── Unused Variable: This variable does not affect the output ports of this module
─────╯
Error: Excess output targets. Function returns 0 results, but 1 targets were given.
     ╭─[ test.sus:897:7 ]
     │
 897 │     when decoder.is_load() : int reg_to, int addr {
     │          ────────┬────────  
     │                  ╰────────── Excess output targets. Function returns 0 results, but 1 targets were given.
     │
     ├─[ test.sus:897:7 ]
     │
 884 │     interface is_load
     │               ───┬───  
     │                  ╰───── Interface 'is_load' defined here
─────╯
Error: Cannot use conditional bingings because the condition isn't an action or a trigger
     ╭─[ test.sus:897:25 ]
     │
 897 │     when decoder.is_load() : int reg_to, int addr {
     │                            ───────────┬──────────  
     │                                       ╰──────────── Cannot use conditional bingings because the condition isn't an action or a trigger
─────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
     ╭─[ test.sus:897:31 ]
     │
 897 │     when decoder.is_load() : int reg_to, int addr {
     │                                  ───┬──  
     │                                     ╰──── Unused Variable: This variable does not affect the output ports of this module
─────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
     ╭─[ test.sus:897:43 ]
     │
 897 │     when decoder.is_load() : int reg_to, int addr {
     │                                              ──┬─  
     │                                                ╰─── Unused Variable: This variable does not affect the output ports of this module
─────╯
Error: Excess output targets. Function returns 0 results, but 1 targets were given.
     ╭─[ test.sus:900:7 ]
     │
 900 │     when decoder.is_arith() : int reg_a, int reg_b, Operator op {
     │          ─────────┬────────  
     │                   ╰────────── Excess output targets. Function returns 0 results, but 1 targets were given.
     │
     ├─[ test.sus:900:7 ]
     │
 885 │     interface is_arith
     │               ────┬───  
     │                   ╰───── Interface 'is_arith' defined here
─────╯
Error: Cannot use conditional bingings because the condition isn't an action or a trigger
     ╭─[ test.sus:900:26 ]
     │
 900 │     when decoder.is_arith() : int reg_a, int reg_b, Operator op {
     │                             ─────────────────┬─────────────────  
     │                                              ╰─────────────────── Cannot use conditional bingings because the condition isn't an action or a trigger
─────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
     ╭─[ test.sus:900:32 ]
     │
 900 │     when decoder.is_arith() : int reg_a, int reg_b, Operator op {
     │                                   ──┬──  
     │                                     ╰──── Unused Variable: This variable does not affect the output ports of this module
─────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
     ╭─[ test.sus:900:43 ]
     │
 900 │     when decoder.is_arith() : int reg_a, int reg_b, Operator op {
     │                                              ──┬──  
     │                                                ╰──── Unused Variable: This variable does not affect the output ports of this module
─────╯
Error: No Global 'Operator' was found.
     ╭─[ test.sus:900:50 ]
     │
 900 │     when decoder.is_arith() : int reg_a, int reg_b, Operator op {
     │                                                     ────┬───  
     │                                                         ╰───── No Global 'Operator' was found.
─────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
     ╭─[ test.sus:900:59 ]
     │
 900 │     when decoder.is_arith() : int reg_a, int reg_b, Operator op {
     │                                                              ─┬  
     │                                                               ╰── Unused Variable: This variable does not affect the output ports of this module
─────╯
Warning: Not Instantiating use_no_main_interface #() due to abstract typing errors
     ╭─[ test.sus:910:8 ]
     │
 910 │ module use_no_main_interface {
     │        ──────────┬──────────  
     │                  ╰──────────── Not Instantiating use_no_main_interface #() due to abstract typing errors
─────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
     ╭─[ test.sus:913:6 ]
     │
 913 │     int x = no_interface_named()
     │         ┬  
     │         ╰── Unused Variable: This variable does not affect the output ports of this module
─────╯
Error: A function call expects this to be a callable interface, the interface `no_main_interface` is not callable
     ╭─[ test.sus:913:10 ]
     │
 913 │     int x = no_interface_named()
     │             ─────────┬────────  
     │                      ╰────────── A function call expects this to be a callable interface, the interface `no_main_interface` is not callable
     │
     ├─[ test.sus:913:10 ]
     │
 906 │ module no_main_interface {
     │        ────────┬────────  
     │                ╰────────── Field 'no_main_interface' declared here
─────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
     ╭─[ test.sus:914:6 ]
     │
 914 │     int y = no_main_interface()
     │         ┬  
     │         ╰── Unused Variable: This variable does not affect the output ports of this module
─────╯
Error: A function call expects this to be a callable interface, the interface `no_main_interface` is not callable
     ╭─[ test.sus:914:10 ]
     │
 914 │     int y = no_main_interface()
     │             ────────┬────────  
     │                     ╰────────── A function call expects this to be a callable interface, the interface `no_main_interface` is not callable
     │
     ├─[ test.sus:914:10 ]
     │
 906 │ module no_main_interface {
     │        ────────┬────────  
     │                ╰────────── Field 'no_main_interface' declared here
─────╯
Warning: Not Instantiating moduleWithBadDeclaration #() due to abstract typing errors
     ╭─[ test.sus:917:8 ]
     │
 917 │ module moduleWithBadDeclaration {
     │        ────────────┬───────────  
     │                    ╰───────────── Not Instantiating moduleWithBadDeclaration #() due to abstract typing errors
─────╯
Error: Typing Error: array size expects 'int #(FROM: _, TO: _)' but was given 'bool #()'
     ╭─[ test.sus:918:6 ]
     │
 918 │     int[true] a
     │         ──┬─  
     │           ╰─── Typing Error: array size expects 'int #(FROM: _, TO: _)' but was given 'bool #()'
─────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
     ╭─[ test.sus:918:12 ]
     │
 918 │     int[true] a
     │               ┬  
     │               ╰── Unused Variable: This variable does not affect the output ports of this module
─────╯
Warning: Not Instantiating moduleWithBadInterface #() due to abstract typing errors
     ╭─[ test.sus:921:8 ]
     │
 921 │ module moduleWithBadInterface {
     │        ───────────┬──────────  
     │                   ╰──────────── Not Instantiating moduleWithBadInterface #() due to abstract typing errors
─────╯
Error: Typing Error: array size expects 'int #(FROM: _, TO: _)' but was given 'bool #()'
     ╭─[ test.sus:922:41 ]
     │
 922 │     interface moduleWithBadInterface : int[true] a
     │                                            ──┬─  
     │                                              ╰─── Typing Error: array size expects 'int #(FROM: _, TO: _)' but was given 'bool #()'
─────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
     ╭─[ test.sus:922:47 ]
     │
 922 │     interface moduleWithBadInterface : int[true] a
     │                                                  ┬  
     │                                                  ╰── Unused Variable: This variable does not affect the output ports of this module
─────╯
Warning: Not Instantiating useModuleWithBadInterface #() due to abstract typing errors
     ╭─[ test.sus:925:8 ]
     │
 925 │ module useModuleWithBadInterface {
     │        ────────────┬────────────  
     │                    ╰────────────── Not Instantiating useModuleWithBadInterface #() due to abstract typing errors
─────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
     ╭─[ test.sus:926:9 ]
     │
 926 │     int[3] xyz
     │            ─┬─  
     │             ╰─── Unused Variable: This variable does not affect the output ports of this module
─────╯
Error: Typing Error: writing the output of this expression expects 'bool #()' but was given 'int #(FROM: _, TO: _)'
     ╭─[ test.sus:929:2 ]
     │
 929 │     xyz[3] = true
     │     ───┬──  
     │        ╰──── Typing Error: writing the output of this expression expects 'bool #()' but was given 'int #(FROM: _, TO: _)'
─────╯
Error: While parsing 'block', parser found a syntax error in a node of type 'ERROR'
     ╭─[ test.sus:935:2 ]
     │
 933 │ ╭─▶ const int SUM_UP #(int SIZE, int[SIZE] DATA) {
     ┆ ┆   
 935 │ │       for I in 0..SIZE {
     │ │       ────────┬───────  
     │ │               ╰───────── While parsing 'block', parser found a syntax error in a node of type 'ERROR'
     ┆ ┆   
 938 │ ├─▶ }
     │ │       
     │ ╰─────── Parent node 'block'
─────╯
Error: No Global 'I' was found.
     ╭─[ test.sus:936:29 ]
     │
 936 │         SUM_UP = SUM_UP + DATA[I]
     │                                ┬  
     │                                ╰── No Global 'I' was found.
─────╯
Warning: Not Instantiating m #() due to abstract typing errors
     ╭─[ test.sus:942:8 ]
     │
 942 │ module m {
     │        ┬  
     │        ╰── Not Instantiating m #() due to abstract typing errors
─────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
     ╭─[ test.sus:943:13 ]
     │
 943 │     gen int[5] DATA
     │                ──┬─  
     │                  ╰─── Unused Variable: This variable does not affect the output ports of this module
─────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
     ╭─[ test.sus:950:10 ]
     │
 950 │     gen int X = SUM_UP #(SIZE: 4, DATA, BEEEP: 3)
     │             ┬  
     │             ╰── Unused Variable: This variable does not affect the output ports of this module
─────╯
Error: SUM_UP has no template argument named 'BEEEP'
     ╭─[ test.sus:950:38 ]
     │
 950 │     gen int X = SUM_UP #(SIZE: 4, DATA, BEEEP: 3)
     │                                         ──┬──  
     │                                           ╰──── SUM_UP has no template argument named 'BEEEP'
     │
     ├─[ test.sus:950:38 ]
     │
 933 │ const int SUM_UP #(int SIZE, int[SIZE] DATA) {
     │           ───┬──  
     │              ╰──── 'SUM_UP' defined here
─────╯
Error: ABC does not name a Type or a Value.
     ╭─[ test.sus:952:8 ]
     │
 952 │     int #(ABC) x
     │           ─┬─  
     │            ╰─── ABC does not name a Type or a Value.
─────╯
Error: int has no template argument named 'ABC'
     ╭─[ test.sus:952:8 ]
     │
 952 │     int #(ABC) x
     │           ─┬─  
     │            ╰─── int has no template argument named 'ABC'
     │
     ├─[ core.sus:13:20 ]
     │
  13 │ __builtin__ struct int #(int FROM, int TO) {}
     │                    ─┬─  
     │                     ╰─── 'int' defined here
─────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
     ╭─[ test.sus:952:13 ]
     │
 952 │     int #(ABC) x
     │                ┬  
     │                ╰── Unused Variable: This variable does not affect the output ports of this module
─────╯
Warning: Clock 'Unconnected_clock_1' has no driver. Non-input clocks require exactly one driving submodule. Defaulting to 'clk'
     ╭─[ test.sus:956:9 ]
     │
 956 │     int[5] a
     │            ┬  
     │            ╰── Clock 'Unconnected_clock_1' has no driver. Non-input clocks require exactly one driving submodule. Defaulting to 'clk'
─────╯
Error: Some parameters of 'a' were still unknown: int #(FROM: ?, TO: ?)[5]
     ╭─[ test.sus:956:9 ]
     │
 956 │     int[5] a
     │            ┬  
     │            ╰── Some parameters of 'a' were still unknown: int #(FROM: ?, TO: ?)[5]
─────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
     ╭─[ test.sus:956:9 ]
     │
 956 │     int[5] a
     │            ┬  
     │            ╰── Unused Variable: This variable does not affect the output ports of this module
─────╯
Error: Some parameters of '_cr_din' were still unknown: int #(FROM: ?, TO: ?)[5]
     ╭─[ test.sus:958:14 ]
     │
 958 │     CrossDomain cr
     │                 ─┬  
     │                  ╰── Some parameters of '_cr_din' were still unknown: int #(FROM: ?, TO: ?)[5]
─────╯
Error: Some parameters of '_cr_dout' were still unknown: int #(FROM: ?, TO: ?)[5]
     ╭─[ test.sus:958:14 ]
     │
 958 │     CrossDomain cr
     │                 ─┬  
     │                  ╰── Some parameters of '_cr_dout' were still unknown: int #(FROM: ?, TO: ?)[5]
─────╯
Error: Some submodule parameters of cr were still unknown: CrossDomain #(T: type int #(FROM: ?, TO: ?)[5])
T can be inferred from:
{*} <: T in T din
{*} = T in T dout

     ╭─[ test.sus:958:14 ]
     │
 958 │     CrossDomain cr
     │                 ─┬  
     │                  ╰── Some submodule parameters of cr were still unknown: CrossDomain #(T: type int #(FROM: ?, TO: ?)[5])
T can be inferred from:
{*} <: T in T din
{*} = T in T dout

─────╯
Error: Some parameters of '_1' were still unknown: int #(FROM: ?, TO: ?)[5]
     ╭─[ test.sus:960:11 ]
     │
 960 │     cr.din = a
     │              ┬  
     │              ╰── Some parameters of '_1' were still unknown: int #(FROM: ?, TO: ?)[5]
─────╯
Warning: Clock 'Unconnected_clock_2' has no driver. Non-input clocks require exactly one driving submodule. Defaulting to 'clk'
     ╭─[ test.sus:961:9 ]
     │
 961 │     int[5] b = cr.dout
     │            ┬  
     │            ╰── Clock 'Unconnected_clock_2' has no driver. Non-input clocks require exactly one driving submodule. Defaulting to 'clk'
─────╯
Error: Some parameters of 'b' were still unknown: int #(FROM: ?, TO: ?)[5]
     ╭─[ test.sus:961:9 ]
     │
 961 │     int[5] b = cr.dout
     │            ┬  
     │            ╰── Some parameters of 'b' were still unknown: int #(FROM: ?, TO: ?)[5]
─────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
     ╭─[ test.sus:961:9 ]
     │
 961 │     int[5] b = cr.dout
     │            ┬  
     │            ╰── Unused Variable: This variable does not affect the output ports of this module
─────╯
Error: Some parameters of '_2' were still unknown: int #(FROM: ?, TO: ?)[5]
     ╭─[ test.sus:961:13 ]
     │
 961 │     int[5] b = cr.dout
     │                ───┬───  
     │                   ╰───── Some parameters of '_2' were still unknown: int #(FROM: ?, TO: ?)[5]
─────╯
Warning: Clock 'Unconnected_clock_1' has no driver. Non-input clocks require exactly one driving submodule. Defaulting to 'clk'
     ╭─[ test.sus:965:9 ]
     │
 965 │     int[5] arr
     │            ─┬─  
     │             ╰─── Clock 'Unconnected_clock_1' has no driver. Non-input clocks require exactly one driving submodule. Defaulting to 'clk'
─────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
     ╭─[ test.sus:965:9 ]
     │
 965 │     int[5] arr
     │            ─┬─  
     │             ╰─── Unused Variable: This variable does not affect the output ports of this module
─────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
     ╭─[ test.sus:974:6 ]
     │
 974 │     int total = adder(arr)
     │         ──┬──  
     │           ╰──── Unused Variable: This variable does not affect the output ports of this module
─────╯
Warning: Not Instantiating implicit_domain_forbidden #() due to abstract typing errors
      ╭─[ test.sus:1005:8 ]
      │
 1005 │ module implicit_domain_forbidden {
      │        ────────────┬────────────  
      │                    ╰────────────── Not Instantiating implicit_domain_forbidden #() due to abstract typing errors
──────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
      ╭─[ test.sus:1006:12 ]
      │
 1006 │     input int bad_port
      │               ────┬───  
      │                   ╰───── Unused Variable: This variable does not affect the output ports of this module
──────╯
Error: When using explicit latency domains, no port is allowed to be declared on the implicit 'default' latency domain.
      ╭─[ test.sus:1008:9 ]
      │
 1008 │     domain bad_domain
      │            ─────┬────  
      │                 ╰────── When using explicit latency domains, no port is allowed to be declared on the implicit 'default' latency domain.
      │
      ├─[ test.sus:1008:9 ]
      │
 1006 │     input int bad_port
      │     ─────────┬────────  
      │              ╰────────── A domain should be explicitly defined before this port
──────╯
Warning: Not Instantiating conflicting_domain_with_port_name #() due to abstract typing errors
      ╭─[ test.sus:1013:8 ]
      │
 1013 │ module conflicting_domain_with_port_name {
      │        ────────────────┬────────────────  
      │                        ╰────────────────── Not Instantiating conflicting_domain_with_port_name #() due to abstract typing errors
──────╯
Error: This declaration conflicts with a previous declaration in the same scope, found domain 'my_domain'
      ╭─[ test.sus:1015:12 ]
      │
 1015 │     input int my_domain
      │               ────┬────  
      │                   ╰────── This declaration conflicts with a previous declaration in the same scope, found domain 'my_domain'
      │
      ├─[ test.sus:1015:12 ]
      │
 1014 │     domain my_domain
      │            ────┬────  
      │                ╰────── Latency Domain 'my_domain' declared here
──────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
      ╭─[ test.sus:1015:12 ]
      │
 1015 │     input int my_domain
      │               ────┬────  
      │                   ╰────── Unused Variable: This variable does not affect the output ports of this module
──────╯
Error: This declaration conflicts with a previous declaration in the same scope, found domain 'my_domain'
      ╭─[ test.sus:1017:9 ]
      │
 1017 │     domain my_domain
      │            ────┬────  
      │                ╰────── This declaration conflicts with a previous declaration in the same scope, found domain 'my_domain'
      │
      ├─[ test.sus:1017:9 ]
      │
 1014 │     domain my_domain
      │            ────┬────  
      │                ╰────── Latency Domain 'my_domain' declared here
──────╯
Warning: Not Instantiating make_infinite_type #() due to abstract typing errors
      ╭─[ test.sus:1027:8 ]
      │
 1027 │ module make_infinite_type {
      │        ─────────┬────────  
      │                 ╰────────── Not Instantiating make_infinite_type #() due to abstract typing errors
──────╯
Error: Typing Error: writing the output of this expression: Creating Infinite Types is Forbidden! expects '?[...]' but was given '?[][...]'
      ╭─[ test.sus:1030:2 ]
      │
 1030 │     mtinf.a = mtinf.b
      │     ───┬───  
      │        ╰───── Typing Error: writing the output of this expression: Creating Infinite Types is Forbidden! expects '?[...]' but was given '?[][...]'
──────╯
Warning: Not Instantiating UseDualPortMem #() due to abstract typing errors
      ╭─[ test.sus:1035:8 ]
      │
 1035 │ module UseDualPortMem {
      │        ───────┬──────  
      │               ╰──────── Not Instantiating UseDualPortMem #() due to abstract typing errors
──────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
      ╭─[ test.sus:1037:8 ]
      │
 1037 │        bool do_write'0,
      │             ────┬───  
      │                 ╰───── Unused Variable: This variable does not affect the output ports of this module
──────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
      ╭─[ test.sus:1039:13 ]
      │
 1039 │        bool[500] data'0 ->
      │                  ──┬─  
      │                    ╰─── Unused Variable: This variable does not affect the output ports of this module
──────╯
Error: No Global 'DualPortMem' was found.
      ╭─[ test.sus:1042:2 ]
      │
 1042 │     DualPortMem #(SIZE: 128, T: type bool[500]) mem
      │     ─────┬─────  
      │          ╰─────── No Global 'DualPortMem' was found.
──────╯
Error: A function call expects this to be an interface, but whatever it was the typechecker couldn't resolve
      ╭─[ test.sus:1044:2 ]
      │
 1044 │     mem.write(do_write, addr, data)
      │     ────┬────  
      │         ╰────── A function call expects this to be an interface, but whatever it was the typechecker couldn't resolve
──────╯
Error: A function call expects this to be an interface, but whatever it was the typechecker couldn't resolve
      ╭─[ test.sus:1046:14 ]
      │
 1046 │     read_data = mem.read(addr)
      │                 ────┬───  
      │                     ╰───── A function call expects this to be an interface, but whatever it was the typechecker couldn't resolve
──────╯
Warning: Not Instantiating example_FIFO #() due to abstract typing errors
      ╭─[ test.sus:1049:8 ]
      │
 1049 │ module example_FIFO {
      │        ──────┬─────  
      │              ╰─────── Not Instantiating example_FIFO #() due to abstract typing errors
──────╯
Error: FIFO has no template argument named 'READY_SLACK'
      ╭─[ test.sus:1050:19 ]
      │
 1050 │     FIFO #(DEPTH: 3, READY_SLACK: 5, T: type int) f
      │                      ─────┬─────  
      │                           ╰─────── FIFO has no template argument named 'READY_SLACK'
      │
      ├─[ memory.sus:131:8 ]
      │
  131 │ module FIFO #(T, int DEPTH, int MAY_PUSH_LATENCY) {
      │        ──┬─  
      │          ╰─── 'FIFO' defined here
──────╯
Warning: Not Instantiating use_Iterator #() due to abstract typing errors
      ╭─[ test.sus:1053:8 ]
      │
 1053 │ module use_Iterator {
      │        ──────┬─────  
      │              ╰─────── Not Instantiating use_Iterator #() due to abstract typing errors
──────╯
Error: Typing Error: function argument expects 'int #(FROM: _, TO: _)' but was given 'bool #()'
      ╭─[ test.sus:1061:20 ]
      │
 1061 │     arrayStream.start(do_start, 10)
      │                       ────┬───  
      │                           ╰───── Typing Error: function argument expects 'int #(FROM: _, TO: _)' but was given 'bool #()'
      │
      ├─[ control_flow.sus:11:47 ]
      │
   11 │     action start'0 : int #(FROM: 0, TO: MAX + 2) up_to'0 {
      │                                                  ──┬──  
      │                                                    ╰──── 'up_to' declared here
──────╯
Error: Excess argument. Function takes 1 args, but 2 were passed.
      ╭─[ test.sus:1061:30 ]
      │
 1061 │     arrayStream.start(do_start, 10)
      │                                 ─┬  
      │                                  ╰── Excess argument. Function takes 1 args, but 2 were passed.
      │
      ├─[ control_flow.sus:11:9 ]
      │
   11 │     action start'0 : int #(FROM: 0, TO: MAX + 2) up_to'0 {
      │            ──┬──  
      │              ╰──── Interface 'start' defined here
──────╯
Error: A function call expects this to be an interface, but whatever it was the typechecker couldn't resolve
      ╭─[ test.sus:1064:31 ]
      │
 1064 │     bool iter_valid, int value = arrayStream.iter()
      │                                  ────────┬───────  
      │                                          ╰───────── A function call expects this to be an interface, but whatever it was the typechecker couldn't resolve
──────╯
Error: No such field 'iter' on Iterator #(MAX: _). Available fields are 'Iterator', 'may_next', 'start', 'next'
      ╭─[ test.sus:1064:43 ]
      │
 1064 │     bool iter_valid, int value = arrayStream.iter()
      │                                              ──┬─  
      │                                                ╰─── No such field 'iter' on Iterator #(MAX: _). Available fields are 'Iterator', 'may_next', 'start', 'next'
      │
      ├─[ control_flow.sus:2:8 ]
      │
    2 │ module Iterator #(int MAX) {
      │        ────┬───  
      │            ╰───── Module 'Iterator' defined here. module Iterator #(int MAX):
domain default:
output state bool may_next'0
action start'0:
	input int #(FROM: 0, TO: MAX + 2) up_to'0
action next'0:
	->
	output int #(FROM: 0, TO: MAX + 1) value'0
	output bool last'0
──────╯
Error: Used 'if' in a non generative context, use 'when' instead
      ╭─[ test.sus:1065:2 ]
      │
 1065 │     if iter_valid {
      │     ─┬  
      │      ╰── Used 'if' in a non generative context, use 'when' instead
──────╯
Error: sizeof #(T: type int #(FROM: ?, TO: ?)[10][10]): For executing compile-time constants, all arguments must be fully specified. The arguments 'T' were not valid
      ╭─[ test.sus:1071:25 ]
      │
 1071 │     gen int INT_ARR_SIZE = sizeof #(T: type int[10][10])
      │                            ──────────────┬──────────────  
      │                                          ╰──────────────── sizeof #(T: type int #(FROM: ?, TO: ?)[10][10]): For executing compile-time constants, all arguments must be fully specified. The arguments 'T' were not valid
──────╯
Error: assert #(C: false): Assertion failed
      ╭─[ test.sus:1081:2 ]
      │
 1081 │     assert #(C: 15 + 3 == 19)
      │     ────────────┬────────────  
      │                 ╰────────────── assert #(C: false): Assertion failed
──────╯
Error: Used 'when' in a generative context, use 'if' instead
      ╭─[ test.sus:1092:2 ]
      │
 1092 │     when WIDTH <= BASE_CASE_SIZE {
      │     ──┬─  
      │       ╰─── Used 'when' in a generative context, use 'if' instead
──────╯
Error: Used 'if' in a non generative context, use 'when' instead
      ╭─[ test.sus:1095:4 ]
      │
 1095 │          if bits[I] {
      │          ─┬  
      │           ╰── Used 'if' in a non generative context, use 'when' instead
──────╯
Error: Used 'if' in a non generative context, use 'when' instead
      ╭─[ test.sus:1097:11 ]
      │
 1097 │          } else if !bits[I] {
      │                 ─┬  
      │                  ╰── Used 'if' in a non generative context, use 'when' instead
──────╯
Error: Used 'when' in a generative context, use 'if' instead
      ╭─[ test.sus:1102:9 ]
      │
 1102 │     } else when WIDTH > BASE_CASE_SIZE {
      │            ──┬─  
      │              ╰─── Used 'when' in a generative context, use 'if' instead
──────╯
Error: This port is not strongly connected to the strongly connected port cluster 'a', 'b'.
An input and output port are strongly connected if there is a direct dependency path from the input port to the output port.
Strongly connected ports are also transitive.
If you do not wish to change your design, then 'virtually' connect this port to the strongly connected cluster by explicitly annotating its absolute latency.
      ╭─[ test.sus:1108:21 ]
      │
 1108 │     interface y : bool c -> bool d
      │                        ┬  
      │                        ╰── This port is not strongly connected to the strongly connected port cluster 'a', 'b'.
An input and output port are strongly connected if there is a direct dependency path from the input port to the output port.
Strongly connected ports are also transitive.
If you do not wish to change your design, then 'virtually' connect this port to the strongly connected cluster by explicitly annotating its absolute latency.
      │
      ├─[ test.sus:1108:21 ]
      │
 1107 │     interface x : bool a -> bool b
      │                        ┬         ┬  
      │                        ╰──────────── 'a' declared here
      │                                  │  
      │                                  ╰── 'b' declared here
──────╯
Error: This port is not strongly connected to the strongly connected port cluster 'a', 'b'.
An input and output port are strongly connected if there is a direct dependency path from the input port to the output port.
Strongly connected ports are also transitive.
If you do not wish to change your design, then 'virtually' connect this port to the strongly connected cluster by explicitly annotating its absolute latency.
      ╭─[ test.sus:1108:31 ]
      │
 1108 │     interface y : bool c -> bool d
      │                                  ┬  
      │                                  ╰── This port is not strongly connected to the strongly connected port cluster 'a', 'b'.
An input and output port are strongly connected if there is a direct dependency path from the input port to the output port.
Strongly connected ports are also transitive.
If you do not wish to change your design, then 'virtually' connect this port to the strongly connected cluster by explicitly annotating its absolute latency.
      │
      ├─[ test.sus:1108:31 ]
      │
 1107 │     interface x : bool a -> bool b
      │                        ┬         ┬  
      │                        ╰──────────── 'a' declared here
      │                                  │  
      │                                  ╰── 'b' declared here
──────╯
Error: This port is not strongly connected to the strongly connected port cluster 'a', 'b'.
An input and output port are strongly connected if there is a direct dependency path from the input port to the output port.
Strongly connected ports are also transitive.
If you do not wish to change your design, then 'virtually' connect this port to the strongly connected cluster by explicitly annotating its absolute latency.
      ╭─[ test.sus:1118:21 ]
      │
 1118 │     interface y : bool c -> bool d
      │                        ┬  
      │                        ╰── This port is not strongly connected to the strongly connected port cluster 'a', 'b'.
An input and output port are strongly connected if there is a direct dependency path from the input port to the output port.
Strongly connected ports are also transitive.
If you do not wish to change your design, then 'virtually' connect this port to the strongly connected cluster by explicitly annotating its absolute latency.
      │
      ├─[ test.sus:1118:21 ]
      │
 1117 │     interface x : bool a -> bool b
      │                        ┬         ┬  
      │                        ╰──────────── 'a' declared here
      │                                  │  
      │                                  ╰── 'b' declared here
──────╯
Error: This port is not strongly connected to the strongly connected port cluster 'a', 'b'.
An input and output port are strongly connected if there is a direct dependency path from the input port to the output port.
Strongly connected ports are also transitive.
If you do not wish to change your design, then 'virtually' connect this port to the strongly connected cluster by explicitly annotating its absolute latency.
      ╭─[ test.sus:1118:31 ]
      │
 1118 │     interface y : bool c -> bool d
      │                                  ┬  
      │                                  ╰── This port is not strongly connected to the strongly connected port cluster 'a', 'b'.
An input and output port are strongly connected if there is a direct dependency path from the input port to the output port.
Strongly connected ports are also transitive.
If you do not wish to change your design, then 'virtually' connect this port to the strongly connected cluster by explicitly annotating its absolute latency.
      │
      ├─[ test.sus:1118:31 ]
      │
 1117 │     interface x : bool a -> bool b
      │                        ┬         ┬  
      │                        ╰──────────── 'a' declared here
      │                                  │  
      │                                  ╰── 'b' declared here
──────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
      ╭─[ test.sus:1122:11 ]
      │
 1122 │     reg bool a_delayed = a
      │              ────┬────  
      │                  ╰────── Unused Variable: This variable does not affect the output ports of this module
──────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
      ╭─[ test.sus:1124:7 ]
      │
 1124 │     bool out_shared = a_delayed ^ c
      │          ─────┬────  
      │               ╰────── Unused Variable: This variable does not affect the output ports of this module
──────╯
Warning: Not Instantiating use_infer_me #() due to abstract typing errors
      ╭─[ test.sus:1131:8 ]
      │
 1131 │ module use_infer_me {
      │        ──────┬─────  
      │              ╰─────── Not Instantiating use_infer_me #() due to abstract typing errors
──────╯
Error: Excess argument. Function takes 1 args, but 2 were passed.
      ╭─[ test.sus:1134:47 ]
      │
 1134 │     out_val = infer_me(in_val | (in_val_2 == 0), in_val_2)
      │                                                  ────┬───  
      │                                                      ╰───── Excess argument. Function takes 1 args, but 2 were passed.
      │ 
 1139 │     interface infer_me : bool x'0 -> bool y'A
      │               ────┬───  
      │                   ╰───── Interface 'infer_me' defined here
──────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
      ╭─[ test.sus:1153:51 ]
      │
 1153 │     trigger request_data'0 : -> int#(FROM: 0, TO: 6) data_received'3
      │                                                      ──────┬──────  
      │                                                            ╰──────── Unused Variable: This variable does not affect the output ports of this module
──────╯
Warning: Unused port 'may_pop'
      ╭─[ test.sus:1155:20 ]
      │
 1155 │     FIFO #(DEPTH: 30) fifo
      │                       ──┬─  
      │                         ╰─── Unused port 'may_pop'
      │
      ├─[ memory.sus:149:17 ]
      │
  149 │     output bool may_pop'0 = read_addr != write_addr
      │                 ───┬───  
      │                    ╰───── Port 'may_pop' declared here
      │
      ├─[ test.sus:1155:20 ]
      │
 1155 │     FIFO #(DEPTH: 30) fifo
      │                       ──┬─  
      │                         ╰─── fifo declared here
──────╯
Warning: Unused port 'pop'
      ╭─[ test.sus:1155:20 ]
      │
 1155 │     FIFO #(DEPTH: 30) fifo
      │                       ──┬─  
      │                         ╰─── Unused port 'pop'
      │
      ├─[ memory.sus:150:12 ]
      │
  150 │     action pop'0 : -> T pop_data'1 {
      │            ─┬─  
      │             ╰─── Port 'pop' declared here
      │
      ├─[ test.sus:1155:20 ]
      │
 1155 │     FIFO #(DEPTH: 30) fifo
      │                       ──┬─  
      │                         ╰─── fifo declared here
──────╯
Warning: Unused port 'pop_data'
      ╭─[ test.sus:1155:20 ]
      │
 1155 │     FIFO #(DEPTH: 30) fifo
      │                       ──┬─  
      │                         ╰─── Unused port 'pop_data'
      │
      ├─[ memory.sus:150:25 ]
      │
  150 │     action pop'0 : -> T pop_data'1 {
      │                         ────┬───  
      │                             ╰───── Port 'pop_data' declared here
      │
      ├─[ test.sus:1155:20 ]
      │
 1155 │     FIFO #(DEPTH: 30) fifo
      │                       ──┬─  
      │                         ╰─── fifo declared here
──────╯
Warning: Unused port 'rst'
      ╭─[ test.sus:1155:20 ]
      │
 1155 │     FIFO #(DEPTH: 30) fifo
      │                       ──┬─  
      │                         ╰─── Unused port 'rst'
      │
      ├─[ memory.sus:157:12 ]
      │
  157 │     action rst {
      │            ─┬─  
      │             ╰─── Port 'rst' declared here
      │
      ├─[ test.sus:1155:20 ]
      │
 1155 │     FIFO #(DEPTH: 30) fifo
      │                       ──┬─  
      │                         ╰─── fifo declared here
──────╯
Error: Conflicting specified latency

a'0
-> _x_x'0 (+0)
-> _x_y'2 (+2)
-> loose_inbetween'2 (+0)
-> _y_x'2 (+0)
-> _y_y'4 (+2)
-> b'4 (+0)

But this was specified as b'3
      ╭─[ test.sus:1176:52 ]
      │
 1176 │     interface inference_edge_case: bool a'0 -> bool b'3
      │                                         ┬             ┬  
      │                                         ╰──────────────── 'a' declared here
      │                                                       │  
      │                                                       ╰── Conflicting specified latency

a'0
-> _x_x'0 (+0)
-> _x_y'2 (+2)
-> loose_inbetween'2 (+0)
-> _y_x'2 (+0)
-> _y_y'4 (+2)
-> b'4 (+0)

But this was specified as b'3
──────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
      ╭─[ test.sus:1193:7 ]
      │
 1193 │     bool in_spec'0 = in_port
      │          ───┬───  
      │             ╰───── Unused Variable: This variable does not affect the output ports of this module
──────╯
Error: Some submodule parameters of infer_me_with_poison_output were still unknown: infer_me_with_poison_output #(N: ?)
N can be inferred as an integer value that is as high as possible, without violating any of the following constraints:
    -N >= i'{*} - o'{*}  ({*} = ? not reached)

      ╭─[ test.sus:1223:19 ]
      │
 1223 │     bool x, bool y = infer_me_with_poison_output(i)
      │                      ─────────────┬─────────────  
      │                                   ╰─────────────── Some submodule parameters of infer_me_with_poison_output were still unknown: infer_me_with_poison_output #(N: ?)
N can be inferred as an integer value that is as high as possible, without violating any of the following constraints:
    -N >= i'{*} - o'{*}  ({*} = ? not reached)

──────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
      ╭─[ test.sus:1228:34 ]
      │
 1228 │     interface __add__ : int#(TO: A) a'0, int #(TO:B) b'0 -> int #(TO: A+B) o'clog2 #(V: 5)
      │                                     ┬  
      │                                     ╰── Unused Variable: This variable does not affect the output ports of this module
──────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
      ╭─[ test.sus:1228:51 ]
      │
 1228 │     interface __add__ : int#(TO: A) a'0, int #(TO:B) b'0 -> int #(TO: A+B) o'clog2 #(V: 5)
      │                                                      ┬  
      │                                                      ╰── Unused Variable: This variable does not affect the output ports of this module
──────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
      ╭─[ test.sus:1239:32 ]
      │
 1239 │ module MultiStateLoop #(T, int II) {
      │                                ─┬  
      │                                 ╰── Unused Variable: This variable does not affect the output ports of this module
──────╯
Error: An action requires a block
      ╭─[ test.sus:1241:3 ]
      │
 1241 │        action next_state'II : T next_state_value
      │        ───┬──  
      │           ╰──── An action requires a block
──────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
      ╭─[ test.sus:1241:28 ]
      │
 1241 │        action next_state'II : T next_state_value
      │                                 ────────┬───────  
      │                                         ╰───────── Unused Variable: This variable does not affect the output ports of this module
──────╯
Error: An action requires a block
      ╭─[ test.sus:1244:2 ]
      │
 1244 │     action request_output : -> trigger output_valid : T result
      │     ───┬──  
      │        ╰──── An action requires a block
──────╯
Error: While parsing 'interface_statement', parser found a syntax error in a node of type 'ERROR'
      ╭─[ test.sus:1244:24 ]
      │
 1244 │     action request_output : -> trigger output_valid : T result
      │     ─────────────────────────────┬────┬───────────────────────  
      │                                  ╰────────────────────────────── Parent node 'interface_statement'
      │                                       │                         
      │                                       ╰───────────────────────── While parsing 'interface_statement', parser found a syntax error in a node of type 'ERROR'
──────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
      ╭─[ test.sus:1244:54 ]
      │
 1244 │     action request_output : -> trigger output_valid : T result
      │                                                         ───┬──  
      │                                                            ╰──── Unused Variable: This variable does not affect the output ports of this module
──────╯
Warning: Not Instantiating use_MultiStateLoop #() due to abstract typing errors
      ╭─[ test.sus:1247:8 ]
      │
 1247 │ module use_MultiStateLoop {
      │        ─────────┬────────  
      │                 ╰────────── Not Instantiating use_MultiStateLoop #() due to abstract typing errors
──────╯
Error: An action requires a block
      ╭─[ test.sus:1251:3 ]
      │
 1251 │        action input_valid : float new_input
      │        ───┬──  
      │           ╰──── An action requires a block
──────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
      ╭─[ test.sus:1251:30 ]
      │
 1251 │        action input_valid : float new_input
      │                                   ────┬────  
      │                                       ╰────── Unused Variable: This variable does not affect the output ports of this module
──────╯
Error: No Global 'trigger' was found.
      ╭─[ test.sus:1253:29 ]
      │
 1253 │     action request_result : -> trigger result_valid : {
      │                                ───┬───  
      │                                   ╰───── No Global 'trigger' was found.
──────╯
Error: While parsing 'interface_statement', parser found a syntax error in a node of type 'ERROR'
      ╭─[ test.sus:1253:50 ]
      │
 1253 │ ╭─▶     action request_result : -> trigger result_valid : {
      │ │                                                       ┬  
      │ │                                                       ╰── While parsing 'interface_statement', parser found a syntax error in a node of type 'ERROR'
      ┆ ┆   
 1255 │ ├─▶     }
      │ │           
      │ ╰─────────── Parent node 'interface_statement'
──────╯
Error: No such field 'process' on MultiStateLoop #(T: type ?[...], II: _). Available fields are 'MultiStateLoop', 'may_process', 'next_state', 'request_output'
      ╭─[ test.sus:1257:12 ]
      │
 1257 │     when loop.process : float cur_state {
      │               ───┬───  
      │                  ╰───── No such field 'process' on MultiStateLoop #(T: type ?[...], II: _). Available fields are 'MultiStateLoop', 'may_process', 'next_state', 'request_output'
      │
      ├─[ test.sus:1257:12 ]
      │
 1239 │ module MultiStateLoop #(T, int II) {
      │        ───────┬──────  
      │               ╰──────── Module 'MultiStateLoop' defined here. module MultiStateLoop #(T, int II):
domain default:
trigger may_process'0:
	output T cur_state
action next_state'II:
	input T next_state_value
action request_output:
	input T result
──────╯
Error: Cannot use conditional bingings because the condition isn't an action or a trigger
      ╭─[ test.sus:1257:20 ]
      │
 1257 │     when loop.process : float cur_state {
      │                       ────────┬────────  
      │                               ╰────────── Cannot use conditional bingings because the condition isn't an action or a trigger
──────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
      ╭─[ test.sus:1257:28 ]
      │
 1257 │     when loop.process : float cur_state {
      │                               ────┬────  
      │                                   ╰────── Unused Variable: This variable does not affect the output ports of this module
──────╯
Error: Typing Error: writing the output of this expression expects 'int #(FROM: _, TO: _)' but was given 'float #()'
      ╭─[ test.sus:1258:3 ]
      │
 1258 │        float next_state = cur_state * cur_state
      │        ────────┬───────  
      │                ╰───────── Typing Error: writing the output of this expression expects 'int #(FROM: _, TO: _)' but was given 'float #()'
──────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
      ╭─[ test.sus:1258:9 ]
      │
 1258 │        float next_state = cur_state * cur_state
      │              ─────┬────  
      │                   ╰────── Unused Variable: This variable does not affect the output ports of this module
──────╯
Error: Typing Error: binop left side expects 'int #(FROM: _, TO: _)' but was given 'float #()'
      ╭─[ test.sus:1258:22 ]
      │
 1258 │        float next_state = cur_state * cur_state
      │                           ────┬────  
      │                               ╰────── Typing Error: binop left side expects 'int #(FROM: _, TO: _)' but was given 'float #()'
──────╯
Error: Typing Error: binop right side expects 'int #(FROM: _, TO: _)' but was given 'float #()'
      ╭─[ test.sus:1258:34 ]
      │
 1258 │        float next_state = cur_state * cur_state
      │                                       ────┬────  
      │                                           ╰────── Typing Error: binop right side expects 'int #(FROM: _, TO: _)' but was given 'float #()'
──────╯
Error: Typing Error: binop left side expects 'int #(FROM: _, TO: _)' but was given 'float #()'
      ╭─[ test.sus:1259:8 ]
      │
 1259 │        when cur_state >= 2.0 {
      │             ────┬────  
      │                 ╰────── Typing Error: binop left side expects 'int #(FROM: _, TO: _)' but was given 'float #()'
──────╯
Error: Typing Error: binop right side expects 'int #(FROM: _, TO: _)' but was given 'float #()'
      ╭─[ test.sus:1259:21 ]
      │
 1259 │        when cur_state >= 2.0 {
      │                          ─┬─  
      │                           ╰─── Typing Error: binop right side expects 'int #(FROM: _, TO: _)' but was given 'float #()'
──────╯
Warning: Clock 'Unconnected_clock_1' has no driver. Non-input clocks require exactly one driving submodule. Defaulting to 'clk'
      ╭─[ test.sus:1266:6 ]
      │
 1266 │     int a = 3
      │         ┬  
      │         ╰── Clock 'Unconnected_clock_1' has no driver. Non-input clocks require exactly one driving submodule. Defaulting to 'clk'
──────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
      ╭─[ test.sus:1266:6 ]
      │
 1266 │     int a = 3
      │         ┬  
      │         ╰── Unused Variable: This variable does not affect the output ports of this module
──────╯
Warning: Clock 'Unconnected_clock_2' has no driver. Non-input clocks require exactly one driving submodule. Defaulting to 'clk'
      ╭─[ test.sus:1267:6 ]
      │
 1267 │     int b = 4
      │         ┬  
      │         ╰── Clock 'Unconnected_clock_2' has no driver. Non-input clocks require exactly one driving submodule. Defaulting to 'clk'
──────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
      ╭─[ test.sus:1267:6 ]
      │
 1267 │     int b = 4
      │         ┬  
      │         ╰── Unused Variable: This variable does not affect the output ports of this module
──────╯
Warning: Clock 'Unconnected_clock_3' has no driver. Non-input clocks require exactly one driving submodule. Defaulting to 'clk'
      ╭─[ test.sus:1269:9 ]
      │
 1269 │     int[4] result = []
      │            ───┬──  
      │               ╰──── Clock 'Unconnected_clock_3' has no driver. Non-input clocks require exactly one driving submodule. Defaulting to 'clk'
──────╯
Error: Some parameters of 'result' were still unknown: int #(FROM: ?, TO: ?)[4]
      ╭─[ test.sus:1269:9 ]
      │
 1269 │     int[4] result = []
      │            ───┬──  
      │               ╰──── Some parameters of 'result' were still unknown: int #(FROM: ?, TO: ?)[4]
──────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
      ╭─[ test.sus:1269:9 ]
      │
 1269 │     int[4] result = []
      │            ───┬──  
      │               ╰──── Unused Variable: This variable does not affect the output ports of this module
──────╯
Error: Some parameters of '_3' were still unknown: int #(FROM: ?, TO: ?)[0]
      ╭─[ test.sus:1269:18 ]
      │
 1269 │     int[4] result = []
      │                     ─┬  
      │                      ╰── Some parameters of '_3' were still unknown: int #(FROM: ?, TO: ?)[0]
──────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
      ╭─[ test.sus:1272:29 ]
      │
 1272 │ module unknownLatency #(int V) {
      │                             ┬  
      │                             ╰── Unused Variable: This variable does not affect the output ports of this module
──────╯
Error: Some submodule parameters of ulat were still unknown: unknownLatency #(V: ?)
V has no acceptable inference candidates

      ╭─[ test.sus:1282:17 ]
      │
 1282 │     unknownLatency ulat
      │                    ──┬─  
      │                      ╰─── Some submodule parameters of ulat were still unknown: unknownLatency #(V: ?)
V has no acceptable inference candidates

──────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
      ╭─[ test.sus:1288:20 ]
      │
 1288 │     interface a: bool x'0 -> bool y'V
      │                       ┬  
      │                       ╰── Unused Variable: This variable does not affect the output ports of this module
──────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
      ╭─[ test.sus:1290:20 ]
      │
 1290 │     interface b: bool p'0 -> bool q'-V
      │                       ┬  
      │                       ╰── Unused Variable: This variable does not affect the output ports of this module
──────╯
Error: Some submodule parameters of inf were still unknown: infer_me_conflicting_directions #(V: ?)
V has no acceptable inference candidates
The following constraints were found, but aren't used for inference here
    V >= x'{*} - q'{*}
    -V >= p'{*} - y'{*}
    V >= p'{*} - q'{*}
    -V >= x'{*} - y'{*}

      ╭─[ test.sus:1296:34 ]
      │
 1296 │     infer_me_conflicting_directions inf
      │                                     ─┬─  
      │                                      ╰─── Some submodule parameters of inf were still unknown: infer_me_conflicting_directions #(V: ?)
V has no acceptable inference candidates
The following constraints were found, but aren't used for inference here
    V >= x'{*} - q'{*}
    -V >= p'{*} - y'{*}
    V >= p'{*} - q'{*}
    -V >= x'{*} - y'{*}

──────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
      ╭─[ test.sus:1303:20 ]
      │
 1303 │     interface a: bool x'0 -> bool y'V
      │                       ┬  
      │                       ╰── Unused Variable: This variable does not affect the output ports of this module
──────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
      ╭─[ test.sus:1305:20 ]
      │
 1305 │     interface b: bool p'0 -> bool q'V+30
      │                       ┬  
      │                       ╰── Unused Variable: This variable does not affect the output ports of this module
──────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
      ╭─[ test.sus:1317:43 ]
      │
 1317 │ module infer_me_with_negative_delta #(int V) {
      │                                           ┬  
      │                                           ╰── Unused Variable: This variable does not affect the output ports of this module
──────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
      ╭─[ test.sus:1318:20 ]
      │
 1318 │     interface a: bool x'V -> bool y'0
      │                       ┬  
      │                       ╰── Unused Variable: This variable does not affect the output ports of this module
──────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
      ╭─[ test.sus:1320:20 ]
      │
 1320 │     interface b: bool p'V -> bool q'0+30
      │                       ┬  
      │                       ╰── Unused Variable: This variable does not affect the output ports of this module
──────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
      ╭─[ test.sus:1332:35 ]
      │
 1332 │ module infer_me_inputs_only #(int V) {
      │                                   ┬  
      │                                   ╰── Unused Variable: This variable does not affect the output ports of this module
──────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
      ╭─[ test.sus:1333:40 ]
      │
 1333 │     interface infer_me_inputs_only : bool a'0, bool b'V
      │                                           ┬  
      │                                           ╰── Unused Variable: This variable does not affect the output ports of this module
──────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
      ╭─[ test.sus:1333:50 ]
      │
 1333 │     interface infer_me_inputs_only : bool a'0, bool b'V
      │                                                     ┬  
      │                                                     ╰── Unused Variable: This variable does not affect the output ports of this module
──────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
      ╭─[ test.sus:1337:44 ]
      │
 1337 │     interface use_infer_me_inputs_only : bool x'0
      │                                               ┬  
      │                                               ╰── Unused Variable: This variable does not affect the output ports of this module
──────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
      ╭─[ test.sus:1340:19 ]
      │
 1340 │     reg reg reg bool y = x
      │                      ┬  
      │                      ╰── Unused Variable: This variable does not affect the output ports of this module
──────╯
Error: Some submodule parameters of infer_me_inputs_only were still unknown: infer_me_inputs_only #(V: ?)
V has no acceptable inference candidates

      ╭─[ test.sus:1342:2 ]
      │
 1342 │     infer_me_inputs_only(x, y)
      │     ──────────┬─────────  
      │               ╰─────────── Some submodule parameters of infer_me_inputs_only were still unknown: infer_me_inputs_only #(V: ?)
V has no acceptable inference candidates

──────╯
Warning: Clock 'Unconnected_clock_1' has no driver. Non-input clocks require exactly one driving submodule. Defaulting to 'clk'
      ╭─[ test.sus:1346:8 ]
      │
 1346 │ module use_ranks {
      │        ────┬────  
      │            ╰────── Clock 'Unconnected_clock_1' has no driver. Non-input clocks require exactly one driving submodule. Defaulting to 'clk'
──────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
      ╭─[ test.sus:1347:14 ]
      │
 1347 │     gen int[15] v = [1, 2, 3, 4, 5, 1, 2, 3, 4, 5, 1, 2, 3, 4, 5]
      │                 ┬  
      │                 ╰── Unused Variable: This variable does not affect the output ports of this module
──────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
      ╭─[ test.sus:1349:14 ]
      │
 1349 │     gen int[15] vv = v + v
      │                 ─┬  
      │                  ╰── Unused Variable: This variable does not affect the output ports of this module
──────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
      ╭─[ test.sus:1351:14 ]
      │
 1351 │     gen int[16] vvv = [1, 2, 4, 8, 1, 2, 4, 8, 1, 2, 4, 8, 1, 2, 4, 6]
      │                 ─┬─  
      │                  ╰─── Unused Variable: This variable does not affect the output ports of this module
──────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
      ╭─[ test.sus:1353:13 ]
      │
 1353 │     gen int[3] qzd = vv + vvv
      │                ─┬─  
      │                 ╰─── Unused Variable: This variable does not affect the output ports of this module
──────╯
Error: Higher Rank array operation's arrays don't match in size: 15, 16
      ╭─[ test.sus:1353:19 ]
      │
 1353 │     gen int[3] qzd = vv + vvv
      │                      ────┬───  
      │                          ╰───── Higher Rank array operation's arrays don't match in size: 15, 16
──────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
      ╭─[ test.sus:1355:16 ]
      │
 1355 │     state int[15] wire_v
      │                   ───┬──  
      │                      ╰──── Unused Variable: This variable does not affect the output ports of this module
──────╯
Warning: Clock 'Unconnected_clock_1' has no driver. Non-input clocks require exactly one driving submodule. Defaulting to 'clk'
      ╭─[ test.sus:1363:9 ]
      │
 1363 │     int[5] vs = [1, 2, 3, 4, 5]
      │            ─┬  
      │             ╰── Clock 'Unconnected_clock_1' has no driver. Non-input clocks require exactly one driving submodule. Defaulting to 'clk'
──────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
      ╭─[ test.sus:1363:9 ]
      │
 1363 │     int[5] vs = [1, 2, 3, 4, 5]
      │            ─┬  
      │             ╰── Unused Variable: This variable does not affect the output ports of this module
──────╯
Warning: Not Instantiating use_FIFO #() due to abstract typing errors
      ╭─[ test.sus:1367:8 ]
      │
 1367 │ module use_FIFO {
      │        ────┬───  
      │            ╰───── Not Instantiating use_FIFO #() due to abstract typing errors
──────╯
Error: FIFO has no template argument named 'READY_SLACK'
      ╭─[ test.sus:1368:23 ]
      │
 1368 │     FIFO #(DEPTH: 53, READY_SLACK: 3) f
      │                       ─────┬─────  
      │                            ╰─────── FIFO has no template argument named 'READY_SLACK'
      │
      ├─[ memory.sus:131:8 ]
      │
  131 │ module FIFO #(T, int DEPTH, int MAY_PUSH_LATENCY) {
      │        ──┬─  
      │          ╰─── 'FIFO' defined here
──────╯
Error: Excess argument. Function takes 1 args, but 2 were passed.
      ╭─[ test.sus:1370:18 ]
      │
 1370 │     f.push(true, 3)
      │                  ┬  
      │                  ╰── Excess argument. Function takes 1 args, but 2 were passed.
      │
      ├─[ memory.sus:143:12 ]
      │
  143 │     action push'0 : T push_data'0 {
      │            ──┬─  
      │              ╰─── Interface 'push' defined here
──────╯
Warning: Not Instantiating write_to_generative_through_when #() due to abstract typing errors
      ╭─[ test.sus:1373:8 ]
      │
 1373 │ module write_to_generative_through_when {
      │        ────────────────┬───────────────  
      │                        ╰───────────────── Not Instantiating write_to_generative_through_when #() due to abstract typing errors
──────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
      ╭─[ test.sus:1374:11 ]
      │
 1374 │     gen bool a
      │              ┬  
      │              ╰── Unused Variable: This variable does not affect the output ports of this module
──────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
      ╭─[ test.sus:1376:7 ]
      │
 1376 │     bool b
      │          ┬  
      │          ╰── Unused Variable: This variable does not affect the output ports of this module
──────╯
Error: Cannot write to compiletime variable through runtime 'when' blocks
      ╭─[ test.sus:1379:3 ]
      │
 1379 │        a = true
      │        ┬  
      │        ╰── Cannot write to compiletime variable through runtime 'when' blocks
      │
      ├─[ test.sus:1379:3 ]
      │
 1374 │     gen bool a
      │              ┬  
      │              ╰── 'a' declared here
      │ 
 1378 │     when b {
      │     ──┬─  
      │       ╰─── Assignment passes through this 'when'
──────╯
Error: This declaration conflicts with a previous declaration in the same scope, found type parameter 'NUM_INPUTS'
      ╭─[ test.sus:1384:13 ]
      │
 1384 │     gen int NUM_INPUTS = 500
      │             ─────┬────  
      │                  ╰────── This declaration conflicts with a previous declaration in the same scope, found type parameter 'NUM_INPUTS'
      │
      ├─[ test.sus:1384:13 ]
      │
 1383 │ module SameNameAsType #(NUM_INPUTS) {
      │                         ─────┬────  
      │                              ╰────── Parameter 'NUM_INPUTS' declared here
──────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
      ╭─[ test.sus:1384:13 ]
      │
 1384 │     gen int NUM_INPUTS = 500
      │             ─────┬────  
      │                  ╰────── Unused Variable: This variable does not affect the output ports of this module
──────╯
Warning: Clock 'Unconnected_clock_1' has no driver. Non-input clocks require exactly one driving submodule. Defaulting to 'clk'
      ╭─[ test.sus:1388:29 ]
      │
 1388 │     FromBits#(T: type int[30]) a
      │                                ┬  
      │                                ╰── Clock 'Unconnected_clock_1' has no driver. Non-input clocks require exactly one driving submodule. Defaulting to 'clk'
──────╯
Error: Some submodule parameters of a were still unknown: FromBits #(T: type int #(FROM: ?, TO: ?)[30])
T can be inferred from:
{*} = T in T value

      ╭─[ test.sus:1388:29 ]
      │
 1388 │     FromBits#(T: type int[30]) a
      │                                ┬  
      │                                ╰── Some submodule parameters of a were still unknown: FromBits #(T: type int #(FROM: ?, TO: ?)[30])
T can be inferred from:
{*} = T in T value

──────╯
Warning: Clock 'Unconnected_clock_2' has no driver. Non-input clocks require exactly one driving submodule. Defaulting to 'clk'
      ╭─[ test.sus:1389:28 ]
      │
 1389 │     ToBits#(T: type bool[60]) b
      │                               ┬  
      │                               ╰── Clock 'Unconnected_clock_2' has no driver. Non-input clocks require exactly one driving submodule. Defaulting to 'clk'
──────╯
Warning: Unused port 'bits'
      ╭─[ test.sus:1389:28 ]
      │
 1389 │     ToBits#(T: type bool[60]) b
      │                               ┬  
      │                               ╰── Unused port 'bits'
      │
      ├─[ conversion.sus:80:55 ]
      │
   80 │     interface ToBits : T value'0 -> bool[sizeof #(T)] bits'0
      │                                                       ──┬─  
      │                                                         ╰─── Port 'bits' declared here
      │
      ├─[ test.sus:1389:28 ]
      │
 1389 │     ToBits#(T: type bool[60]) b
      │                               ┬  
      │                               ╰── b declared here
──────╯
Warning: Unused port 'value'
      ╭─[ test.sus:1389:28 ]
      │
 1389 │     ToBits#(T: type bool[60]) b
      │                               ┬  
      │                               ╰── Unused port 'value'
      │
      ├─[ conversion.sus:80:26 ]
      │
   80 │     interface ToBits : T value'0 -> bool[sizeof #(T)] bits'0
      │                          ──┬──  
      │                            ╰──── Port 'value' declared here
      │
      ├─[ test.sus:1389:28 ]
      │
 1389 │     ToBits#(T: type bool[60]) b
      │                               ┬  
      │                               ╰── b declared here
──────╯
Warning: Clock 'Unconnected_clock_3' has no driver. Non-input clocks require exactly one driving submodule. Defaulting to 'clk'
      ╭─[ test.sus:1390:32 ]
      │
 1390 │     ToBits#(T: type int[3][3][5]) c
      │                                   ┬  
      │                                   ╰── Clock 'Unconnected_clock_3' has no driver. Non-input clocks require exactly one driving submodule. Defaulting to 'clk'
──────╯
Error: Some submodule parameters of c were still unknown: ToBits #(T: type int #(FROM: ?, TO: ?)[3][3][5])
T can be inferred from:
{*} <: T in T value

      ╭─[ test.sus:1390:32 ]
      │
 1390 │     ToBits#(T: type int[3][3][5]) c
      │                                   ┬  
      │                                   ╰── Some submodule parameters of c were still unknown: ToBits #(T: type int #(FROM: ?, TO: ?)[3][3][5])
T can be inferred from:
{*} <: T in T value

──────╯
Warning: Clock 'Unconnected_clock_1' has no driver. Non-input clocks require exactly one driving submodule. Defaulting to 'clk'
      ╭─[ test.sus:1394:28 ]
      │
 1394 │     int#(FROM: 0, TO: 255)[2] a
      │                               ┬  
      │                               ╰── Clock 'Unconnected_clock_1' has no driver. Non-input clocks require exactly one driving submodule. Defaulting to 'clk'
──────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
      ╭─[ test.sus:1394:28 ]
      │
 1394 │     int#(FROM: 0, TO: 255)[2] a
      │                               ┬  
      │                               ╰── Unused Variable: This variable does not affect the output ports of this module
──────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
      ╭─[ test.sus:1396:10 ]
      │
 1396 │     gen int SZ = sizeof #(T: type int#(FROM: 0, TO: 256*256))
      │             ─┬  
      │              ╰── Unused Variable: This variable does not affect the output ports of this module
──────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
      ╭─[ test.sus:1398:6 ]
      │
 1398 │     int b = Transmute#(T2: type int#(FROM: 0, TO: 256*256)) (a)
      │         ┬  
      │         ╰── Unused Variable: This variable does not affect the output ports of this module
──────╯
Warning: Clock 'Unconnected_clock_2' has no driver. Non-input clocks require exactly one driving submodule. Defaulting to 'clk'
      ╭─[ test.sus:1400:24 ]
      │
 1400 │     int #(FROM: 5, TO: 3) v
      │                           ┬  
      │                           ╰── Clock 'Unconnected_clock_2' has no driver. Non-input clocks require exactly one driving submodule. Defaulting to 'clk'
──────╯
Error: The type of 'v' is invalid! int #(FROM: 5, TO: 3)
      ╭─[ test.sus:1400:24 ]
      │
 1400 │     int #(FROM: 5, TO: 3) v
      │                           ┬  
      │                           ╰── The type of 'v' is invalid! int #(FROM: 5, TO: 3)
──────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
      ╭─[ test.sus:1400:24 ]
      │
 1400 │     int #(FROM: 5, TO: 3) v
      │                           ┬  
      │                           ╰── Unused Variable: This variable does not affect the output ports of this module
──────╯
Warning: Clock 'Unconnected_clock_1' has no driver. Non-input clocks require exactly one driving submodule. Defaulting to 'clk'
      ╭─[ test.sus:1415:7 ]
      │
 1415 │     bool b
      │          ┬  
      │          ╰── Clock 'Unconnected_clock_1' has no driver. Non-input clocks require exactly one driving submodule. Defaulting to 'clk'
──────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
      ╭─[ test.sus:1415:7 ]
      │
 1415 │     bool b
      │          ┬  
      │          ╰── Unused Variable: This variable does not affect the output ports of this module
──────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
      ╭─[ test.sus:1423:25 ]
      │
 1423 │     when submod.beep : int x {
      │                            ┬  
      │                            ╰── Unused Variable: This variable does not affect the output ports of this module
──────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
      ╭─[ test.sus:1424:7 ]
      │
 1424 │        int y = x
      │            ┬  
      │            ╰── Unused Variable: This variable does not affect the output ports of this module
──────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
      ╭─[ test.sus:1433:18 ]
      │
 1433 │     gen int[10][20] INTS
      │                     ──┬─  
      │                       ╰─── Unused Variable: This variable does not affect the output ports of this module
──────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
      ╭─[ test.sus:1435:10 ]
      │
 1435 │     for int i in 0..10 {
      │             ┬  
      │             ╰── Unused Variable: This variable does not affect the output ports of this module
──────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
      ╭─[ test.sus:1436:11 ]
      │
 1436 │        for int j in 0..20 {
      │                ┬  
      │                ╰── Unused Variable: This variable does not affect the output ports of this module
──────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
      ╭─[ test.sus:1443:17 ]
      │
 1443 │     gen int[5][30] SUBSLICE = INTS[11:14][2:5]
      │                    ────┬───  
      │                        ╰───── Unused Variable: This variable does not affect the output ports of this module
──────╯
Warning: Clock 'Unconnected_clock_1' has no driver. Non-input clocks require exactly one driving submodule. Defaulting to 'clk'
      ╭─[ test.sus:1445:6 ]
      │
 1445 │     int x = 3
      │         ┬  
      │         ╰── Clock 'Unconnected_clock_1' has no driver. Non-input clocks require exactly one driving submodule. Defaulting to 'clk'
──────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
      ╭─[ test.sus:1445:6 ]
      │
 1445 │     int x = 3
      │         ┬  
      │         ╰── Unused Variable: This variable does not affect the output ports of this module
──────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
      ╭─[ test.sus:1447:6 ]
      │
 1447 │     int y = 1
      │         ┬  
      │         ╰── Unused Variable: This variable does not affect the output ports of this module
──────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
      ╭─[ test.sus:1449:6 ]
      │
 1449 │     int z = INTS[x][y]
      │         ┬  
      │         ╰── Unused Variable: This variable does not affect the output ports of this module
──────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
      ╭─[ test.sus:1451:12 ]
      │
 1451 │     int[3][4] w = INTS[x+:4][y-:3]
      │               ┬  
      │               ╰── Unused Variable: This variable does not affect the output ports of this module
──────╯
Warning: Clock 'Unconnected_clock_2' has no driver. Non-input clocks require exactly one driving submodule. Defaulting to 'clk'
      ╭─[ test.sus:1453:25 ]
      │
 1453 │     int#(FROM:0, TO: 6)[0] zero_slice = INTS[5][4:4]
      │                            ─────┬────  
      │                                 ╰────── Clock 'Unconnected_clock_2' has no driver. Non-input clocks require exactly one driving submodule. Defaulting to 'clk'
──────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
      ╭─[ test.sus:1453:25 ]
      │
 1453 │     int#(FROM:0, TO: 6)[0] zero_slice = INTS[5][4:4]
      │                            ─────┬────  
      │                                 ╰────── Unused Variable: This variable does not affect the output ports of this module
──────╯
Error: Some parameters of 'INTS_3' were still unknown: int #(FROM: ?, TO: ?)[0]
      ╭─[ test.sus:1453:38 ]
      │
 1453 │     int#(FROM:0, TO: 6)[0] zero_slice = INTS[5][4:4]
      │                                         ──────┬─────  
      │                                               ╰─────── Some parameters of 'INTS_3' were still unknown: int #(FROM: ?, TO: ?)[0]
──────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
      ╭─[ test.sus:1458:18 ]
      │
 1458 │     gen int[10][20] INTS
      │                     ──┬─  
      │                       ╰─── Unused Variable: This variable does not affect the output ports of this module
──────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
      ╭─[ test.sus:1460:10 ]
      │
 1460 │     for int i in 0..10 {
      │             ┬  
      │             ╰── Unused Variable: This variable does not affect the output ports of this module
──────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
      ╭─[ test.sus:1461:11 ]
      │
 1461 │        for int j in 0..20 {
      │                ┬  
      │                ╰── Unused Variable: This variable does not affect the output ports of this module
──────╯
Error: Attempting to write to this slice 11:14 (length 3) with an array of length 0.
      ╭─[ test.sus:1466:7 ]
      │
 1466 │     INTS[11:14][2:5] = []
      │          ──┬──  
      │            ╰──── Attempting to write to this slice 11:14 (length 3) with an array of length 0.
──────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
      ╭─[ test.sus:1471:18 ]
      │
 1471 │     gen int[10][20] INTS
      │                     ──┬─  
      │                       ╰─── Unused Variable: This variable does not affect the output ports of this module
──────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
      ╭─[ test.sus:1473:10 ]
      │
 1473 │     for int i in 0..10 {
      │             ┬  
      │             ╰── Unused Variable: This variable does not affect the output ports of this module
──────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
      ╭─[ test.sus:1474:11 ]
      │
 1474 │        for int j in 0..20 {
      │                ┬  
      │                ╰── Unused Variable: This variable does not affect the output ports of this module
──────╯
Warning: Clock 'Unconnected_clock_1' has no driver. Non-input clocks require exactly one driving submodule. Defaulting to 'clk'
      ╭─[ test.sus:1479:25 ]
      │
 1479 │     int#(FROM:0, TO: 6)[0] negative_slice = INTS[5][4:3]
      │                            ───────┬──────  
      │                                   ╰──────── Clock 'Unconnected_clock_1' has no driver. Non-input clocks require exactly one driving submodule. Defaulting to 'clk'
──────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
      ╭─[ test.sus:1479:25 ]
      │
 1479 │     int#(FROM:0, TO: 6)[0] negative_slice = INTS[5][4:3]
      │                            ───────┬──────  
      │                                   ╰──────── Unused Variable: This variable does not affect the output ports of this module
──────╯
Error: Slice 4:3 has a negative length.
      ╭─[ test.sus:1479:50 ]
      │
 1479 │     int#(FROM:0, TO: 6)[0] negative_slice = INTS[5][4:3]
      │                                                     ─┬─  
      │                                                      ╰─── Slice 4:3 has a negative length.
──────╯
Warning: Not Instantiating duplicate_port_names #() due to abstract typing errors
      ╭─[ test.sus:1501:8 ]
      │
 1501 │ module duplicate_port_names {
      │        ──────────┬─────────  
      │                  ╰─────────── Not Instantiating duplicate_port_names #() due to abstract typing errors
──────╯
Error: Duplicate port 'port_a' declaration
      ╭─[ test.sus:1505:14 ]
      │
 1505 │        input bool port_a
      │                   ───┬──  
      │                      ╰──── Duplicate port 'port_a' declaration
      │
      ├─[ test.sus:1505:14 ]
      │
 1503 │        output bool port_a
      │                    ───┬──  
      │                       ╰──── port 'port_a' declared here
──────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
      ╭─[ test.sus:1505:14 ]
      │
 1505 │        input bool port_a
      │                   ───┬──  
      │                      ╰──── Unused Variable: This variable does not affect the output ports of this module
──────╯
Error: Duplicate interface 'interf' declaration
      ╭─[ test.sus:1511:13 ]
      │
 1511 │        interface interf
      │                  ───┬──  
      │                     ╰──── Duplicate interface 'interf' declaration
      │
      ├─[ test.sus:1511:13 ]
      │
 1509 │        interface interf
      │                  ───┬──  
      │                     ╰──── interface 'interf' declared here
──────╯
Error: Duplicate interface 'port_interf' declaration
      ╭─[ test.sus:1514:12 ]
      │
 1514 │     interface port_interf: bool port_interf
      │               ─────┬─────       ─────┬─────  
      │                    ╰───────────────────────── Duplicate interface 'port_interf' declaration
      │                                      │       
      │                                      ╰─────── port 'port_interf' declared here
──────╯
Error: This declaration conflicts with a previous declaration in the same scope, found interface 'port_interf'
      ╭─[ test.sus:1514:30 ]
      │
 1514 │     interface port_interf: bool port_interf
      │               ─────┬─────       ─────┬─────  
      │                    ╰───────────────────────── 'port_interf' declared here
      │                                      │       
      │                                      ╰─────── This declaration conflicts with a previous declaration in the same scope, found interface 'port_interf'
──────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
      ╭─[ test.sus:1514:30 ]
      │
 1514 │     interface port_interf: bool port_interf
      │                                 ─────┬─────  
      │                                      ╰─────── Unused Variable: This variable does not affect the output ports of this module
──────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
      ╭─[ test.sus:1516:27 ]
      │
 1516 │        interface proooot: bool preeee
      │                                ───┬──  
      │                                   ╰──── Unused Variable: This variable does not affect the output ports of this module
──────╯
Error: Duplicate interface 'preeee' declaration
      ╭─[ test.sus:1518:13 ]
      │
 1518 │        interface preeee
      │                  ───┬──  
      │                     ╰──── Duplicate interface 'preeee' declaration
      │
      ├─[ test.sus:1518:13 ]
      │
 1516 │        interface proooot: bool preeee
      │                                ───┬──  
      │                                   ╰──── port 'preeee' declared here
──────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
      ╭─[ test.sus:1523:12 ]
      │
 1523 │     gen float f = 1.0E+8
      │               ┬  
      │               ╰── Unused Variable: This variable does not affect the output ports of this module
──────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
      ╭─[ test.sus:1524:15 ]
      │
 1524 │     gen float nf = -1.3
      │               ─┬  
      │                ╰── Unused Variable: This variable does not affect the output ports of this module
──────╯
Warning: Clock 'Unconnected_clock_1' has no driver. Non-input clocks require exactly one driving submodule. Defaulting to 'clk'
      ╭─[ test.sus:1526:11 ]
      │
 1526 │     float ff = f
      │           ─┬  
      │            ╰── Clock 'Unconnected_clock_1' has no driver. Non-input clocks require exactly one driving submodule. Defaulting to 'clk'
──────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
      ╭─[ test.sus:1526:11 ]
      │
 1526 │     float ff = f
      │           ─┬  
      │            ╰── Unused Variable: This variable does not affect the output ports of this module
──────╯
Warning: Clock 'Unconnected_clock_2' has no driver. Non-input clocks require exactly one driving submodule. Defaulting to 'clk'
      ╭─[ test.sus:1527:11 ]
      │
 1527 │     float fff = 0.0625
      │           ─┬─  
      │            ╰─── Clock 'Unconnected_clock_2' has no driver. Non-input clocks require exactly one driving submodule. Defaulting to 'clk'
──────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
      ╭─[ test.sus:1527:11 ]
      │
 1527 │     float fff = 0.0625
      │           ─┬─  
      │            ╰─── Unused Variable: This variable does not affect the output ports of this module
──────╯
Warning: Clock 'Unconnected_clock_3' has no driver. Non-input clocks require exactly one driving submodule. Defaulting to 'clk'
      ╭─[ test.sus:1529:14 ]
      │
 1529 │     float[5] many_floats = [0.7, 0.9, -0.7, -0.9, 0.1]
      │              ─────┬─────  
      │                   ╰─────── Clock 'Unconnected_clock_3' has no driver. Non-input clocks require exactly one driving submodule. Defaulting to 'clk'
──────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
      ╭─[ test.sus:1529:14 ]
      │
 1529 │     float[5] many_floats = [0.7, 0.9, -0.7, -0.9, 0.1]
      │              ─────┬─────  
      │                   ╰─────── Unused Variable: This variable does not affect the output ports of this module
──────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
      ╭─[ test.sus:1533:18 ]
      │
 1533 │     gen float[5] floats = [0.3, 0.4, 0.2, 0.3, 0.5]
      │                  ───┬──  
      │                     ╰──── Unused Variable: This variable does not affect the output ports of this module
──────╯
Warning: Clock 'Unconnected_clock_1' has no driver. Non-input clocks require exactly one driving submodule. Defaulting to 'clk'
      ╭─[ test.sus:1536:14 ]
      │
 1536 │     float[5] fs = floats
      │              ─┬  
      │               ╰── Clock 'Unconnected_clock_1' has no driver. Non-input clocks require exactly one driving submodule. Defaulting to 'clk'
──────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
      ╭─[ test.sus:1536:14 ]
      │
 1536 │     float[5] fs = floats
      │              ─┬  
      │               ╰── Unused Variable: This variable does not affect the output ports of this module
──────╯
Warning: Clock 'Unconnected_clock_2' has no driver. Non-input clocks require exactly one driving submodule. Defaulting to 'clk'
      ╭─[ test.sus:1538:9 ]
      │
 1538 │     int y = 3
      │         ┬  
      │         ╰── Clock 'Unconnected_clock_2' has no driver. Non-input clocks require exactly one driving submodule. Defaulting to 'clk'
──────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
      ╭─[ test.sus:1538:9 ]
      │
 1538 │     int y = 3
      │         ┬  
      │         ╰── Unused Variable: This variable does not affect the output ports of this module
──────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
      ╭─[ test.sus:1539:11 ]
      │
 1539 │     float x = floats[y]
      │           ┬  
      │           ╰── Unused Variable: This variable does not affect the output ports of this module
──────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
      ╭─[ test.sus:1543:13 ]
      │
 1543 │     input bool x
      │                ┬  
      │                ╰── Unused Variable: This variable does not affect the output ports of this module
──────╯
Error: This port is not strongly connected to the strongly connected port cluster 'x'.
An input and output port are strongly connected if there is a direct dependency path from the input port to the output port.
Strongly connected ports are also transitive.
If you do not wish to change your design, then 'virtually' connect this port to the strongly connected cluster by explicitly annotating its absolute latency.
      ╭─[ test.sus:1544:10 ]
      │
 1544 │     trigger t : bool b
      │             ┬  
      │             ╰── This port is not strongly connected to the strongly connected port cluster 'x'.
An input and output port are strongly connected if there is a direct dependency path from the input port to the output port.
Strongly connected ports are also transitive.
If you do not wish to change your design, then 'virtually' connect this port to the strongly connected cluster by explicitly annotating its absolute latency.
      │
      ├─[ test.sus:1544:10 ]
      │
 1543 │     input bool x
      │                ┬  
      │                ╰── 'x' declared here
──────╯
Error: This port is not strongly connected to the strongly connected port cluster 'x'.
An input and output port are strongly connected if there is a direct dependency path from the input port to the output port.
Strongly connected ports are also transitive.
If you do not wish to change your design, then 'virtually' connect this port to the strongly connected cluster by explicitly annotating its absolute latency.
      ╭─[ test.sus:1544:19 ]
      │
 1544 │     trigger t : bool b
      │                      ┬  
      │                      ╰── This port is not strongly connected to the strongly connected port cluster 'x'.
An input and output port are strongly connected if there is a direct dependency path from the input port to the output port.
Strongly connected ports are also transitive.
If you do not wish to change your design, then 'virtually' connect this port to the strongly connected cluster by explicitly annotating its absolute latency.
      │
      ├─[ test.sus:1544:19 ]
      │
 1543 │     input bool x
      │                ┬  
      │                ╰── 'x' declared here
──────╯
Error: This port is not strongly connected to the strongly connected port cluster 'xx'.
An input and output port are strongly connected if there is a direct dependency path from the input port to the output port.
Strongly connected ports are also transitive.
If you do not wish to change your design, then 'virtually' connect this port to the strongly connected cluster by explicitly annotating its absolute latency.
      ╭─[ test.sus:1551:14 ]
      │
 1551 │     output bool b
      │                 ┬  
      │                 ╰── This port is not strongly connected to the strongly connected port cluster 'xx'.
An input and output port are strongly connected if there is a direct dependency path from the input port to the output port.
Strongly connected ports are also transitive.
If you do not wish to change your design, then 'virtually' connect this port to the strongly connected cluster by explicitly annotating its absolute latency.
      │
      ├─[ test.sus:1551:14 ]
      │
 1550 │     input bool xx
      │                ─┬  
      │                 ╰── 'xx' declared here
──────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
      ╭─[ test.sus:1554:18 ]
      │
 1554 │     when w.t : bool c {
      │                     ┬  
      │                     ╰── Unused Variable: This variable does not affect the output ports of this module
──────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
      ╭─[ test.sus:1562:13 ]
      │
 1562 │     input bool b
      │                ┬  
      │                ╰── Unused Variable: This variable does not affect the output ports of this module
──────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
      ╭─[ test.sus:1564:11 ]
      │
 1564 │        for int SZ in 1..4 {
      │                ─┬  
      │                 ╰── Unused Variable: This variable does not affect the output ports of this module
──────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
      ╭─[ test.sus:1565:13 ]
      │
 1565 │          bool[SZ] x = Repeat(false)
      │                   ┬  
      │                   ╰── Unused Variable: This variable does not affect the output ports of this module
──────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
      ╭─[ test.sus:1566:13 ]
      │
 1566 │          bool[SZ] y = x
      │                   ┬  
      │                   ╰── Unused Variable: This variable does not affect the output ports of this module
──────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
      ╭─[ test.sus:1568:26 ]
      │
 1568 │          int#(FROM: 0, TO: SZ) u = 0
      │                                ┬  
      │                                ╰── Unused Variable: This variable does not affect the output ports of this module
──────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
      ╭─[ test.sus:1569:8 ]
      │
 1569 │          int v = u
      │              ┬  
      │              ╰── Unused Variable: This variable does not affect the output ports of this module
──────╯
Warning: Clock 'Unconnected_clock_1' has no driver. Non-input clocks require exactly one driving submodule. Defaulting to 'clk'
      ╭─[ test.sus:1575:11 ]
      │
 1575 │     bool[50] b = 50'b010100_100110
      │              ┬  
      │              ╰── Clock 'Unconnected_clock_1' has no driver. Non-input clocks require exactly one driving submodule. Defaulting to 'clk'
──────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
      ╭─[ test.sus:1575:11 ]
      │
 1575 │     bool[50] b = 50'b010100_100110
      │              ┬  
      │              ╰── Unused Variable: This variable does not affect the output ports of this module
──────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
      ╭─[ test.sus:1576:16 ]
      │
 1576 │     gen bool[100] bb = 100'h035434____ae_fb_CDE07846847
      │                   ─┬  
      │                    ╰── Unused Variable: This variable does not affect the output ports of this module
──────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
      ╭─[ test.sus:1577:16 ]
      │
 1577 │     gen bool[101] bbb
      │                   ─┬─  
      │                    ╰─── Unused Variable: This variable does not affect the output ports of this module
──────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
      ╭─[ test.sus:1578:10 ]
      │
 1578 │     for int i in 0..100 {
      │             ┬  
      │             ╰── Unused Variable: This variable does not affect the output ports of this module
──────╯
Warning: Clock 'Unconnected_clock_2' has no driver. Non-input clocks require exactly one driving submodule. Defaulting to 'clk'
      ╭─[ test.sus:1581:12 ]
      │
 1581 │     bool[100] ob = 100'o035434_074647
      │               ─┬  
      │                ╰── Clock 'Unconnected_clock_2' has no driver. Non-input clocks require exactly one driving submodule. Defaulting to 'clk'
──────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
      ╭─[ test.sus:1581:12 ]
      │
 1581 │     bool[100] ob = 100'o035434_074647
      │               ─┬  
      │                ╰── Unused Variable: This variable does not affect the output ports of this module
──────╯
Warning: Clock 'Unconnected_clock_1' has no driver. Non-input clocks require exactly one driving submodule. Defaulting to 'clk'
      ╭─[ test.sus:1585:8 ]
      │
 1585 │     float x = 0.5
      │           ┬  
      │           ╰── Clock 'Unconnected_clock_1' has no driver. Non-input clocks require exactly one driving submodule. Defaulting to 'clk'
──────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
      ╭─[ test.sus:1585:8 ]
      │
 1585 │     float x = 0.5
      │           ┬  
      │           ╰── Unused Variable: This variable does not affect the output ports of this module
──────╯
Warning: Clock 'Unconnected_clock_2' has no driver. Non-input clocks require exactly one driving submodule. Defaulting to 'clk'
      ╭─[ test.sus:1586:8 ]
      │
 1586 │     float y = 0.5e9
      │           ┬  
      │           ╰── Clock 'Unconnected_clock_2' has no driver. Non-input clocks require exactly one driving submodule. Defaulting to 'clk'
──────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
      ╭─[ test.sus:1586:8 ]
      │
 1586 │     float y = 0.5e9
      │           ┬  
      │           ╰── Unused Variable: This variable does not affect the output ports of this module
──────╯
Warning: Clock 'Unconnected_clock_3' has no driver. Non-input clocks require exactly one driving submodule. Defaulting to 'clk'
      ╭─[ test.sus:1587:9 ]
      │
 1587 │     double a = 0.5d
      │            ┬  
      │            ╰── Clock 'Unconnected_clock_3' has no driver. Non-input clocks require exactly one driving submodule. Defaulting to 'clk'
──────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
      ╭─[ test.sus:1587:9 ]
      │
 1587 │     double a = 0.5d
      │            ┬  
      │            ╰── Unused Variable: This variable does not affect the output ports of this module
──────╯
Warning: Clock 'Unconnected_clock_4' has no driver. Non-input clocks require exactly one driving submodule. Defaulting to 'clk'
      ╭─[ test.sus:1588:9 ]
      │
 1588 │     double b = 0.5e9d
      │            ┬  
      │            ╰── Clock 'Unconnected_clock_4' has no driver. Non-input clocks require exactly one driving submodule. Defaulting to 'clk'
──────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
      ╭─[ test.sus:1588:9 ]
      │
 1588 │     double b = 0.5e9d
      │            ┬  
      │            ╰── Unused Variable: This variable does not affect the output ports of this module
──────╯
Warning: Not Instantiating use_module_taking_strings #() due to abstract typing errors
      ╭─[ test.sus:1595:8 ]
      │
 1595 │ module use_module_taking_strings {
      │        ────────────┬────────────  
      │                    ╰────────────── Not Instantiating use_module_taking_strings #() due to abstract typing errors
──────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
      ╭─[ test.sus:1596:13 ]
      │
 1596 │     gen string S = "BEEEP BOOP"
      │                ┬  
      │                ╰── Unused Variable: This variable does not affect the output ports of this module
──────╯
Error: 'string' cannot be non-generative.
      ╭─[ test.sus:1597:2 ]
      │
 1597 │     string S2 = "BAAP \"BAAP"
      │     ────┬────  
      │         ╰────── 'string' cannot be non-generative.
──────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
      ╭─[ test.sus:1597:9 ]
      │
 1597 │     string S2 = "BAAP \"BAAP"
      │            ─┬  
      │             ╰── Unused Variable: This variable does not affect the output ports of this module
──────╯
Warning: Clock 'Unconnected_clock_1' has no driver. Non-input clocks require exactly one driving submodule. Defaulting to 'clk'
      ╭─[ test.sus:1602:6 ]
      │
 1602 │     int x = 0
      │         ┬  
      │         ╰── Clock 'Unconnected_clock_1' has no driver. Non-input clocks require exactly one driving submodule. Defaulting to 'clk'
──────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
      ╭─[ test.sus:1602:6 ]
      │
 1602 │     int x = 0
      │         ┬  
      │         ╰── Unused Variable: This variable does not affect the output ports of this module
──────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
      ╭─[ test.sus:1603:10 ]
      │
 1603 │     bool[0] as_bits = UIntToBits(x)
      │             ───┬───  
      │                ╰───── Unused Variable: This variable does not affect the output ports of this module
──────╯
Warning: Clock 'Unconnected_clock_2' has no driver. Non-input clocks require exactly one driving submodule. Defaulting to 'clk'
      ╭─[ test.sus:1604:9 ]
      │
 1604 │     int[5] zero_sized_arr = [0, 0, 0, 0, 0]
      │            ───────┬──────  
      │                   ╰──────── Clock 'Unconnected_clock_2' has no driver. Non-input clocks require exactly one driving submodule. Defaulting to 'clk'
──────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
      ╭─[ test.sus:1604:9 ]
      │
 1604 │     int[5] zero_sized_arr = [0, 0, 0, 0, 0]
      │            ───────┬──────  
      │                   ╰──────── Unused Variable: This variable does not affect the output ports of this module
──────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
      ╭─[ test.sus:1605:13 ]
      │
 1605 │     gen int[5] zero_sized_gen = [0, 0, 0, 0, 0]
      │                ───────┬──────  
      │                       ╰──────── Unused Variable: This variable does not affect the output ports of this module
──────╯
Warning: Clock 'Unconnected_clock_3' has no driver. Non-input clocks require exactly one driving submodule. Defaulting to 'clk'
      ╭─[ test.sus:1606:9 ]
      │
 1606 │     int[5] make_real = zero_sized_gen
      │            ────┬────  
      │                ╰────── Clock 'Unconnected_clock_3' has no driver. Non-input clocks require exactly one driving submodule. Defaulting to 'clk'
──────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
      ╭─[ test.sus:1606:9 ]
      │
 1606 │     int[5] make_real = zero_sized_gen
      │            ────┬────  
      │                ╰────── Unused Variable: This variable does not affect the output ports of this module
──────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
      ╭─[ test.sus:1607:6 ]
      │
 1607 │     int addr = 4
      │         ──┬─  
      │           ╰─── Unused Variable: This variable does not affect the output ports of this module
──────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
      ╭─[ test.sus:1608:6 ]
      │
 1608 │     int a = zero_sized_gen[addr]
      │         ┬  
      │         ╰── Unused Variable: This variable does not affect the output ports of this module
──────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
      ╭─[ test.sus:1609:6 ]
      │
 1609 │     int b = zero_sized_arr[addr]
      │         ┬  
      │         ╰── Unused Variable: This variable does not affect the output ports of this module
──────╯
Warning: Clock 'Unconnected_clock_1' has no driver. Non-input clocks require exactly one driving submodule. Defaulting to 'clk'
      ╭─[ test.sus:1613:24 ]
      │
 1613 │     int#(FROM: 0, TO: 13) unsigned_val
      │                           ──────┬─────  
      │                                 ╰─────── Clock 'Unconnected_clock_1' has no driver. Non-input clocks require exactly one driving submodule. Defaulting to 'clk'
──────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
      ╭─[ test.sus:1613:24 ]
      │
 1613 │     int#(FROM: 0, TO: 13) unsigned_val
      │                           ──────┬─────  
      │                                 ╰─────── Unused Variable: This variable does not affect the output ports of this module
──────╯
Warning: Clock 'Unconnected_clock_2' has no driver. Non-input clocks require exactly one driving submodule. Defaulting to 'clk'
      ╭─[ test.sus:1614:26 ]
      │
 1614 │     int#(FROM: -20, TO: 13) signed_val
      │                             ─────┬────  
      │                                  ╰────── Clock 'Unconnected_clock_2' has no driver. Non-input clocks require exactly one driving submodule. Defaulting to 'clk'
──────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
      ╭─[ test.sus:1614:26 ]
      │
 1614 │     int#(FROM: -20, TO: 13) signed_val
      │                             ─────┬────  
      │                                  ╰────── Unused Variable: This variable does not affect the output ports of this module
──────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
      ╭─[ test.sus:1616:23 ]
      │
 1616 │     int#(FROM: 5, TO: 8) dynamic_mod
      │                          ─────┬─────  
      │                               ╰─────── Unused Variable: This variable does not affect the output ports of this module
──────╯
Warning: The result of this expression is not used. Only function calls can return nothing. 
      ╭─[ test.sus:1619:2 ]
      │
 1619 │     unsigned_val mod 8
      │     ─────────┬────────  
      │              ╰────────── The result of this expression is not used. Only function calls can return nothing. 
──────╯
Warning: The result of this expression is not used. Only function calls can return nothing. 
      ╭─[ test.sus:1620:2 ]
      │
 1620 │     unsigned_val mod 4
      │     ─────────┬────────  
      │              ╰────────── The result of this expression is not used. Only function calls can return nothing. 
──────╯
Warning: The result of this expression is not used. Only function calls can return nothing. 
      ╭─[ test.sus:1621:2 ]
      │
 1621 │     unsigned_val mod 2
      │     ─────────┬────────  
      │              ╰────────── The result of this expression is not used. Only function calls can return nothing. 
──────╯
Warning: The result of this expression is not used. Only function calls can return nothing. 
      ╭─[ test.sus:1622:2 ]
      │
 1622 │     signed_val mod 8
      │     ────────┬───────  
      │             ╰───────── The result of this expression is not used. Only function calls can return nothing. 
──────╯
Warning: The result of this expression is not used. Only function calls can return nothing. 
      ╭─[ test.sus:1623:2 ]
      │
 1623 │     signed_val mod 4
      │     ────────┬───────  
      │             ╰───────── The result of this expression is not used. Only function calls can return nothing. 
──────╯
Warning: The result of this expression is not used. Only function calls can return nothing. 
      ╭─[ test.sus:1624:2 ]
      │
 1624 │     signed_val mod 2
      │     ────────┬───────  
      │             ╰───────── The result of this expression is not used. Only function calls can return nothing. 
──────╯
Warning: The result of this expression is not used. Only function calls can return nothing. 
      ╭─[ test.sus:1626:2 ]
      │
 1626 │     unsigned_val mod 1
      │     ─────────┬────────  
      │              ╰────────── The result of this expression is not used. Only function calls can return nothing. 
──────╯
Warning: The result of this expression is not used. Only function calls can return nothing. 
      ╭─[ test.sus:1627:2 ]
      │
 1627 │     signed_val mod 1
      │     ────────┬───────  
      │             ╰───────── The result of this expression is not used. Only function calls can return nothing. 
──────╯
Warning: The result of this expression is not used. Only function calls can return nothing. 
      ╭─[ test.sus:1631:2 ]
      │
 1631 │     unsigned_val mod 13
      │     ─────────┬─────────  
      │              ╰─────────── The result of this expression is not used. Only function calls can return nothing. 
──────╯
Warning: The result of this expression is not used. Only function calls can return nothing. 
      ╭─[ test.sus:1633:2 ]
      │
 1633 │     unsigned_val + 1 mod 13
      │     ───────────┬───────────  
      │                ╰───────────── The result of this expression is not used. Only function calls can return nothing. 
──────╯
Warning: The result of this expression is not used. Only function calls can return nothing. 
      ╭─[ test.sus:1635:2 ]
      │
 1635 │     unsigned_val + 2 mod 13
      │     ───────────┬───────────  
      │                ╰───────────── The result of this expression is not used. Only function calls can return nothing. 
──────╯
Warning: The result of this expression is not used. Only function calls can return nothing. 
      ╭─[ test.sus:1636:2 ]
      │
 1636 │     unsigned_val + 13 mod 13
      │     ────────────┬───────────  
      │                 ╰───────────── The result of this expression is not used. Only function calls can return nothing. 
──────╯
Warning: The result of this expression is not used. Only function calls can return nothing. 
      ╭─[ test.sus:1638:2 ]
      │
 1638 │     unsigned_val + 14 mod 13
      │     ────────────┬───────────  
      │                 ╰───────────── The result of this expression is not used. Only function calls can return nothing. 
──────╯
Warning: The result of this expression is not used. Only function calls can return nothing. 
      ╭─[ test.sus:1642:2 ]
      │
 1642 │     unsigned_val - 1 mod 13
      │     ───────────┬───────────  
      │                ╰───────────── The result of this expression is not used. Only function calls can return nothing. 
──────╯
Warning: The result of this expression is not used. Only function calls can return nothing. 
      ╭─[ test.sus:1644:2 ]
      │
 1644 │     unsigned_val - 2 mod 13
      │     ───────────┬───────────  
      │                ╰───────────── The result of this expression is not used. Only function calls can return nothing. 
──────╯
Warning: The result of this expression is not used. Only function calls can return nothing. 
      ╭─[ test.sus:1645:2 ]
      │
 1645 │     unsigned_val - 13 mod 13
      │     ────────────┬───────────  
      │                 ╰───────────── The result of this expression is not used. Only function calls can return nothing. 
──────╯
Warning: The result of this expression is not used. Only function calls can return nothing. 
      ╭─[ test.sus:1647:2 ]
      │
 1647 │     unsigned_val - 14 mod 13
      │     ────────────┬───────────  
      │                 ╰───────────── The result of this expression is not used. Only function calls can return nothing. 
──────╯
Warning: The result of this expression is not used. Only function calls can return nothing. 
      ╭─[ test.sus:1650:2 ]
      │
 1650 │     unsigned_val mod dynamic_mod
      │     ──────────────┬─────────────  
      │                   ╰─────────────── The result of this expression is not used. Only function calls can return nothing. 
──────╯
Warning: Clock 'Unconnected_clock_1' has no driver. Non-input clocks require exactly one driving submodule. Defaulting to 'clk'
      ╭─[ test.sus:1674:25 ]
      │
 1674 │     int#(FROM: 10, TO: 11) a = 10
      │                            ┬  
      │                            ╰── Clock 'Unconnected_clock_1' has no driver. Non-input clocks require exactly one driving submodule. Defaulting to 'clk'
──────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
      ╭─[ test.sus:1674:25 ]
      │
 1674 │     int#(FROM: 10, TO: 11) a = 10
      │                            ┬  
      │                            ╰── Unused Variable: This variable does not affect the output ports of this module
──────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
      ╭─[ test.sus:1675:23 ]
      │
 1675 │     int#(FROM: 3, TO: 4) b = 3
      │                          ┬  
      │                          ╰── Unused Variable: This variable does not affect the output ports of this module
──────╯
Warning: The result of this expression is not used. Only function calls can return nothing. 
      ╭─[ test.sus:1677:2 ]
      │
 1677 │     a % b
      │     ──┬──  
      │       ╰──── The result of this expression is not used. Only function calls can return nothing. 
──────╯
Warning: The result of this expression is not used. Only function calls can return nothing. 
      ╭─[ test.sus:1678:2 ]
      │
 1678 │     -a % b
      │     ───┬──  
      │        ╰──── The result of this expression is not used. Only function calls can return nothing. 
──────╯
Warning: The result of this expression is not used. Only function calls can return nothing. 
      ╭─[ test.sus:1679:2 ]
      │
 1679 │     a % -b
      │     ───┬──  
      │        ╰──── The result of this expression is not used. Only function calls can return nothing. 
──────╯
Warning: The result of this expression is not used. Only function calls can return nothing. 
      ╭─[ test.sus:1680:2 ]
      │
 1680 │     -a % -b
      │     ───┬───  
      │        ╰───── The result of this expression is not used. Only function calls can return nothing. 
──────╯
Warning: Clock 'Unconnected_clock_1' has no driver. Non-input clocks require exactly one driving submodule. Defaulting to 'clk'
      ╭─[ test.sus:1684:16 ]
      │
 1684 │     state bool[5] A
      │                   ┬  
      │                   ╰── Clock 'Unconnected_clock_1' has no driver. Non-input clocks require exactly one driving submodule. Defaulting to 'clk'
──────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
      ╭─[ test.sus:1684:16 ]
      │
 1684 │     state bool[5] A
      │                   ┬  
      │                   ╰── Unused Variable: This variable does not affect the output ports of this module
──────╯
Warning: Not Instantiating NonGenerativeSliceBoundsMustNotICE #() due to abstract typing errors
      ╭─[ test.sus:1706:8 ]
      │
 1706 │ module NonGenerativeSliceBoundsMustNotICE {
      │        ─────────────────┬────────────────  
      │                         ╰────────────────── Not Instantiating NonGenerativeSliceBoundsMustNotICE #() due to abstract typing errors
──────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
      ╭─[ test.sus:1707:14 ]
      │
 1707 │     bool[20] arr
      │              ─┬─  
      │               ╰─── Unused Variable: This variable does not affect the output ports of this module
──────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
      ╭─[ test.sus:1709:9 ]
      │
 1709 │     int x = 3
      │         ┬  
      │         ╰── Unused Variable: This variable does not affect the output ports of this module
──────╯
Warning: The result of this expression is not used. Only function calls can return nothing. 
      ╭─[ test.sus:1710:5 ]
      │
 1710 │     arr[3 +: x]
      │     ─────┬─────  
      │          ╰─────── The result of this expression is not used. Only function calls can return nothing. 
──────╯
Error: The width of a part-select cannot be non-generative
      ╭─[ test.sus:1710:14 ]
      │
 1710 │     arr[3 +: x]
      │              ┬  
      │              ╰── The width of a part-select cannot be non-generative
──────╯
Warning: The result of this expression is not used. Only function calls can return nothing. 
      ╭─[ test.sus:1711:5 ]
      │
 1711 │     arr[x:5]
      │     ────┬───  
      │         ╰───── The result of this expression is not used. Only function calls can return nothing. 
──────╯
Error: A slice bound cannot be non-generative
      ╭─[ test.sus:1711:9 ]
      │
 1711 │     arr[x:5]
      │         ┬  
      │         ╰── A slice bound cannot be non-generative
──────╯
Warning: The result of this expression is not used. Only function calls can return nothing. 
      ╭─[ test.sus:1712:5 ]
      │
 1712 │     arr[5:x]
      │     ────┬───  
      │         ╰───── The result of this expression is not used. Only function calls can return nothing. 
──────╯
Error: A slice bound cannot be non-generative
      ╭─[ test.sus:1712:11 ]
      │
 1712 │     arr[5:x]
      │           ┬  
      │           ╰── A slice bound cannot be non-generative
──────╯
Warning: The result of this expression is not used. Only function calls can return nothing. 
      ╭─[ test.sus:1713:5 ]
      │
 1713 │     arr[x:]
      │     ───┬───  
      │        ╰───── The result of this expression is not used. Only function calls can return nothing. 
──────╯
Error: A slice bound cannot be non-generative
      ╭─[ test.sus:1713:9 ]
      │
 1713 │     arr[x:]
      │         ┬  
      │         ╰── A slice bound cannot be non-generative
──────╯
Warning: The result of this expression is not used. Only function calls can return nothing. 
      ╭─[ test.sus:1714:5 ]
      │
 1714 │     arr[:x]
      │     ───┬───  
      │        ╰───── The result of this expression is not used. Only function calls can return nothing. 
──────╯
Error: A slice bound cannot be non-generative
      ╭─[ test.sus:1714:10 ]
      │
 1714 │     arr[:x]
      │          ┬  
      │          ╰── A slice bound cannot be non-generative
──────╯
Warning: Clock 'Unconnected_clock_1' has no driver. Non-input clocks require exactly one driving submodule. Defaulting to 'clk'
      ╭─[ test.sus:1718:21 ]
      │
 1718 │     InstantiatesItself x
      │                        ┬  
      │                        ╰── Clock 'Unconnected_clock_1' has no driver. Non-input clocks require exactly one driving submodule. Defaulting to 'clk'
──────╯
Error: InstantiatesItself #() depends on itself! Infinite Submodule Recursion is not allowed.
Current Instantiation Stack:
- InstantiatesItself #()
- InstantiatesItself #()
      ╭─[ test.sus:1718:21 ]
      │
 1718 │     InstantiatesItself x
      │                        ┬  
      │                        ╰── InstantiatesItself #() depends on itself! Infinite Submodule Recursion is not allowed.
Current Instantiation Stack:
- InstantiatesItself #()
- InstantiatesItself #()
──────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
      ╭─[ test.sus:1731:56 ]
      │
 1731 │     interface ReceiveZerosArray : int#(FROM: 0, TO: 1)[2] values
      │                                                           ───┬──  
      │                                                              ╰──── Unused Variable: This variable does not affect the output ports of this module
──────╯
Warning: Clock 'Unconnected_clock_1' has no driver. Non-input clocks require exactly one driving submodule. Defaulting to 'clk'
      ╭─[ test.sus:1735:9 ]
      │
 1735 │     int[2] zeros = [0, 0]
      │            ──┬──  
      │              ╰──── Clock 'Unconnected_clock_1' has no driver. Non-input clocks require exactly one driving submodule. Defaulting to 'clk'
──────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
      ╭─[ test.sus:1735:9 ]
      │
 1735 │     int[2] zeros = [0, 0]
      │            ──┬──  
      │              ╰──── Unused Variable: This variable does not affect the output ports of this module
──────╯
Warning: Clock 'Unconnected_clock_2' has no driver. Non-input clocks require exactly one driving submodule. Defaulting to 'clk'
      ╭─[ test.sus:1736:30 ]
      │
 1736 │     int#(FROM: -5, TO: 6)[2] vs = [0, 0]
      │                              ─┬  
      │                               ╰── Clock 'Unconnected_clock_2' has no driver. Non-input clocks require exactly one driving submodule. Defaulting to 'clk'
──────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
      ╭─[ test.sus:1736:30 ]
      │
 1736 │     int#(FROM: -5, TO: 6)[2] vs = [0, 0]
      │                              ─┬  
      │                               ╰── Unused Variable: This variable does not affect the output ports of this module
──────╯
Warning: Clock 'Unconnected_clock_3' has no driver. Non-input clocks require exactly one driving submodule. Defaulting to 'clk'
      ╭─[ test.sus:1737:2 ]
      │
 1737 │     ReceiveZerosArray([0, 0])
      │     ────────┬────────  
      │             ╰────────── Clock 'Unconnected_clock_3' has no driver. Non-input clocks require exactly one driving submodule. Defaulting to 'clk'
──────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
      ╭─[ test.sus:1739:19 ]
      │
 1739 │     int[4][6][7][20] manyzeros
      │                      ────┬────  
      │                          ╰────── Unused Variable: This variable does not affect the output ports of this module
──────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
      ╭─[ test.sus:1742:9 ]
      │
 1742 │     int[2] nums = [5, 9]
      │            ──┬─  
      │              ╰─── Unused Variable: This variable does not affect the output ports of this module
──────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
      ╭─[ test.sus:1743:9 ]
      │
 1743 │     int[2] sums = nums + [0, 0] + zeros + manyzeros[1][5:7][4][3]
      │            ──┬─  
      │              ╰─── Unused Variable: This variable does not affect the output ports of this module
──────╯
Warning: Clock 'Unconnected_clock_1' has no driver. Non-input clocks require exactly one driving submodule. Defaulting to 'clk'
      ╭─[ test.sus:1747:8 ]
      │
 1747 │     int[] a = [3, 6, 7]
      │           ┬  
      │           ╰── Clock 'Unconnected_clock_1' has no driver. Non-input clocks require exactly one driving submodule. Defaulting to 'clk'
──────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
      ╭─[ test.sus:1747:8 ]
      │
 1747 │     int[] a = [3, 6, 7]
      │           ┬  
      │           ╰── Unused Variable: This variable does not affect the output ports of this module
──────╯
Warning: Clock 'Unconnected_clock_2' has no driver. Non-input clocks require exactly one driving submodule. Defaulting to 'clk'
      ╭─[ test.sus:1750:8 ]
      │
 1750 │     int[] b
      │           ┬  
      │           ╰── Clock 'Unconnected_clock_2' has no driver. Non-input clocks require exactly one driving submodule. Defaulting to 'clk'
──────╯
Error: Some parameters of 'b' were still unknown: int #(FROM: 3, TO: 6)[_]
      ╭─[ test.sus:1750:8 ]
      │
 1750 │     int[] b
      │           ┬  
      │           ╰── Some parameters of 'b' were still unknown: int #(FROM: 3, TO: 6)[_]
──────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
      ╭─[ test.sus:1750:8 ]
      │
 1750 │     int[] b
      │           ┬  
      │           ╰── Unused Variable: This variable does not affect the output ports of this module
──────╯
Warning: The result of this expression is not used. Only function calls can return nothing. 
      ╭─[ test.sus:1764:2 ]
      │
 1764 │     nextPow2#(V: -1)
      │     ────────┬───────  
      │             ╰───────── The result of this expression is not used. Only function calls can return nothing. 
──────╯
Error: nextPow2 #(V: -1): V must be positive! Found -1
      ╭─[ test.sus:1764:2 ]
      │
 1764 │     nextPow2#(V: -1)
      │     ────────┬───────  
      │             ╰───────── nextPow2 #(V: -1): V must be positive! Found -1
──────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
      ╭─[ test.sus:1768:13 ]
      │
 1768 │     input bool y
      │                ┬  
      │                ╰── Unused Variable: This variable does not affect the output ports of this module
──────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
      ╭─[ test.sus:1769:16 ]
      │
 1769 │     split bool[5] x
      │                   ┬  
      │                   ╰── Unused Variable: This variable does not affect the output ports of this module
──────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
      ╭─[ test.sus:1770:15 ]
      │
 1770 │     split bool[] x_unknowns
      │                  ─────┬────  
      │                       ╰────── Unused Variable: This variable does not affect the output ports of this module
──────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
      ╭─[ test.sus:1771:15 ]
      │
 1771 │     split bool[] x_with_latency'4
      │                  ───────┬──────  
      │                         ╰──────── Unused Variable: This variable does not affect the output ports of this module
──────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
      ╭─[ test.sus:1776:10 ]
      │
 1776 │     for int i in 1..5 {
      │             ┬  
      │             ╰── Unused Variable: This variable does not affect the output ports of this module
──────╯
Warning: Clock 'Unconnected_clock_1' has no driver. Non-input clocks require exactly one driving submodule. Defaulting to 'clk'
      ╭─[ test.sus:1815:17 ]
      │
 1815 │     ModWithDomains mwd
      │                    ─┬─  
      │                     ╰─── Clock 'Unconnected_clock_1' has no driver. Non-input clocks require exactly one driving submodule. Defaulting to 'clk'
──────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
      ╭─[ test.sus:1817:25 ]
      │
 1817 │     when mwd.b_trig : bool d {}
      │                            ┬  
      │                            ╰── Unused Variable: This variable does not affect the output ports of this module
──────╯
Warning: Not Instantiating GenerativeCannotHaveLatencyDeclaration #() due to abstract typing errors
      ╭─[ test.sus:1822:8 ]
      │
 1822 │ module GenerativeCannotHaveLatencyDeclaration {
      │        ───────────────────┬──────────────────  
      │                           ╰──────────────────── Not Instantiating GenerativeCannotHaveLatencyDeclaration #() due to abstract typing errors
──────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
      ╭─[ test.sus:1823:10 ]
      │
 1823 │     gen int beep'4
      │             ──┬─  
      │               ╰─── Unused Variable: This variable does not affect the output ports of this module
──────╯
Error: Generative Declarations may not have a latency specifier
      ╭─[ test.sus:1823:15 ]
      │
 1823 │     gen int beep'4
      │                  ┬  
      │                  ╰── Generative Declarations may not have a latency specifier
──────╯
Error: No Unique assignment for Port Latency. Options are:
- '100 from x'99
- '101 from y'99
Try specifying an explicit latency or rework the module to remove this ambiguity
      ╭─[ test.sus:1830:14 ]
      │
 1830 │     output bool b // error should be on 'b'
      │                 ┬  
      │                 ╰── No Unique assignment for Port Latency. Options are:
- '100 from x'99
- '101 from y'99
Try specifying an explicit latency or rework the module to remove this ambiguity
      │
      ├─[ test.sus:1830:14 ]
      │
 1827 │     input bool x
      │                ┬  
      │                ╰── 'x' declared here
 1828 │     input bool y
      │                ┬  
      │                ╰── 'y' declared here
──────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
      ╭─[ test.sus:1839:13 ]
      │
 1839 │     gen int BEEE
      │             ──┬─  
      │               ╰─── Unused Variable: This variable does not affect the output ports of this module
──────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
      ╭─[ test.sus:1840:13 ]
      │
 1840 │     gen int BOOO = BEEE
      │             ──┬─  
      │               ╰─── Unused Variable: This variable does not affect the output ports of this module
──────╯
Error: 'BEEE' is Unset!
      ╭─[ test.sus:1840:20 ]
      │
 1840 │     gen int BOOO = BEEE
      │                    ──┬─  
      │                      ╰─── 'BEEE' is Unset!
      │
      ├─[ test.sus:1840:20 ]
      │
 1839 │     gen int BEEE
      │             ──┬─  
      │               ╰─── 'BEEE' declared here
──────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
      ╭─[ test.sus:1843:16 ]
      │
 1843 │     gen int[5] array
      │                ──┬──  
      │                  ╰──── Unused Variable: This variable does not affect the output ports of this module
──────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
      ╭─[ test.sus:1844:13 ]
      │
 1844 │     gen int x = array[3]
      │             ┬  
      │             ╰── Unused Variable: This variable does not affect the output ports of this module
──────╯
Error: 'array[3]' is Unset!
      ╭─[ test.sus:1844:17 ]
      │
 1844 │     gen int x = array[3]
      │                 ────┬───  
      │                     ╰───── 'array[3]' is Unset!
      │
      ├─[ test.sus:1844:17 ]
      │
 1843 │     gen int[5] array
      │                ──┬──  
      │                  ╰──── 'array' declared here
──────╯
Warning: Not Instantiating RegressionForBadPort #() due to abstract typing errors
      ╭─[ test.sus:1847:8 ]
      │
 1847 │ module RegressionForBadPort {
      │        ──────────┬─────────  
      │                  ╰─────────── Not Instantiating RegressionForBadPort #() due to abstract typing errors
──────╯
Error: No Global '' was found.
      ╭─[ test.sus:1848:19 ]
      │
 1848 │     trigger my_trig'-
      │                      │ 
      │                      ╰─ No Global '' was found.
──────╯
Error: While parsing 'template_global', parser found a missing field in the field 'item' of type 'identifier'
      ╭─[ test.sus:1848:19 ]
      │
 1848 │     trigger my_trig'-
      │                      │ 
      │                      ╰─ While parsing 'template_global', parser found a missing field in the field 'item' of type 'identifier'
      │                      │ 
      │                      ╰─ Parent node 'template_global'
──────╯
Warning: Clock 'Unconnected_clock_1' has no driver. Non-input clocks require exactly one driving submodule. Defaulting to 'clk'
      ╭─[ test.sus:1852:6 ]
      │
 1852 │     int x = IntNarrow#(FROM: 0, TO: 1)(5)
      │         ┬  
      │         ╰── Clock 'Unconnected_clock_1' has no driver. Non-input clocks require exactly one driving submodule. Defaulting to 'clk'
──────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
      ╭─[ test.sus:1852:6 ]
      │
 1852 │     int x = IntNarrow#(FROM: 0, TO: 1)(5)
      │         ┬  
      │         ╰── Unused Variable: This variable does not affect the output ports of this module
──────╯
Warning: Clock 'Unconnected_clock_2' has no driver. Non-input clocks require exactly one driving submodule. Defaulting to 'clk'
      ╭─[ test.sus:1853:6 ]
      │
 1853 │     int y = IntNarrow#(FROM: -3, TO: 6)(0)
      │         ┬  
      │         ╰── Clock 'Unconnected_clock_2' has no driver. Non-input clocks require exactly one driving submodule. Defaulting to 'clk'
──────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
      ╭─[ test.sus:1853:6 ]
      │
 1853 │     int y = IntNarrow#(FROM: -3, TO: 6)(0)
      │         ┬  
      │         ╰── Unused Variable: This variable does not affect the output ports of this module
──────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
      ╭─[ test.sus:1857:10 ]
      │
 1857 │     for int I in -10..10 {
      │             ┬  
      │             ╰── Unused Variable: This variable does not affect the output ports of this module
──────╯
Warning: Clock 'Unconnected_clock_1' has no driver. Non-input clocks require exactly one driving submodule. Defaulting to 'clk'
      ╭─[ test.sus:1858:7 ]
      │
 1858 │        int j = I
      │            ┬  
      │            ╰── Clock 'Unconnected_clock_1' has no driver. Non-input clocks require exactly one driving submodule. Defaulting to 'clk'
──────╯
Warning: Unused Variable: This variable does not affect the output ports of this module
      ╭─[ test.sus:1858:7 ]
      │
 1858 │        int j = I
      │            ┬  
      │            ╰── Unused Variable: This variable does not affect the output ports of this module
──────╯
Error: Output clock 'this_clock_out' has no driver. output clocks require exactly one driving submodule.
      ╭─[ test.sus:1869:15 ]
      │
 1869 │     output clock this_clock_out
      │                  ───────┬──────  
      │                         ╰──────── Output clock 'this_clock_out' has no driver. output clocks require exactly one driving submodule.
──────╯
Warning: Clock 'Unconnected_clock_1' has no driver. Non-input clocks require exactly one driving submodule. Defaulting to 'clk'
      ╭─[ test.sus:1888:42 ]
      │
 1888 │     LatencyOffset#(T: type bool, OFFSET: 3) pos
      │                                             ─┬─  
      │                                              ╰─── Clock 'Unconnected_clock_1' has no driver. Non-input clocks require exactly one driving submodule. Defaulting to 'clk'
──────╯
Warning: Unused port 'din'
      ╭─[ test.sus:1888:42 ]
      │
 1888 │     LatencyOffset#(T: type bool, OFFSET: 3) pos
      │                                             ─┬─  
      │                                              ╰─── Unused port 'din'
      │
      ├─[ core.sus:55:33 ]
      │
   55 │     interface LatencyOffset : T din'0 -> T dout'OFFSET
      │                                 ─┬─  
      │                                  ╰─── Port 'din' declared here
      │
      ├─[ test.sus:1888:42 ]
      │
 1888 │     LatencyOffset#(T: type bool, OFFSET: 3) pos
      │                                             ─┬─  
      │                                              ╰─── pos declared here
──────╯
Warning: Unused port 'dout'
      ╭─[ test.sus:1888:42 ]
      │
 1888 │     LatencyOffset#(T: type bool, OFFSET: 3) pos
      │                                             ─┬─  
      │                                              ╰─── Unused port 'dout'
      │
      ├─[ core.sus:55:44 ]
      │
   55 │     interface LatencyOffset : T din'0 -> T dout'OFFSET
      │                                            ──┬─  
      │                                              ╰─── Port 'dout' declared here
      │
      ├─[ test.sus:1888:42 ]
      │
 1888 │     LatencyOffset#(T: type bool, OFFSET: 3) pos
      │                                             ─┬─  
      │                                              ╰─── pos declared here
──────╯
Warning: Clock 'Unconnected_clock_2' has no driver. Non-input clocks require exactly one driving submodule. Defaulting to 'clk'
      ╭─[ test.sus:1889:43 ]
      │
 1889 │     LatencyOffset#(T: type bool, OFFSET: -3) neg
      │                                              ─┬─  
      │                                               ╰─── Clock 'Unconnected_clock_2' has no driver. Non-input clocks require exactly one driving submodule. Defaulting to 'clk'
──────╯
Warning: Unused port 'din'
      ╭─[ test.sus:1889:43 ]
      │
 1889 │     LatencyOffset#(T: type bool, OFFSET: -3) neg
      │                                              ─┬─  
      │                                               ╰─── Unused port 'din'
      │
      ├─[ core.sus:55:33 ]
      │
   55 │     interface LatencyOffset : T din'0 -> T dout'OFFSET
      │                                 ─┬─  
      │                                  ╰─── Port 'din' declared here
      │
      ├─[ test.sus:1889:43 ]
      │
 1889 │     LatencyOffset#(T: type bool, OFFSET: -3) neg
      │                                              ─┬─  
      │                                               ╰─── neg declared here
──────╯
Warning: Unused port 'dout'
      ╭─[ test.sus:1889:43 ]
      │
 1889 │     LatencyOffset#(T: type bool, OFFSET: -3) neg
      │                                              ─┬─  
      │                                               ╰─── Unused port 'dout'
      │
      ├─[ core.sus:55:44 ]
      │
   55 │     interface LatencyOffset : T din'0 -> T dout'OFFSET
      │                                            ──┬─  
      │                                              ╰─── Port 'dout' declared here
      │
      ├─[ test.sus:1889:43 ]
      │
 1889 │     LatencyOffset#(T: type bool, OFFSET: -3) neg
      │                                              ─┬─  
      │                                               ╰─── neg declared here
──────╯
[ERROR sus_compiler::codegen] Cannot codegen generative #() due to errors!
[ERROR sus_compiler::codegen] Cannot codegen assignment_producer #() due to errors!
[ERROR sus_compiler::codegen] Cannot codegen test_various_assignments #() due to errors!
[ERROR sus_compiler::codegen] Cannot codegen multiply_add_with_latencies #() due to errors!
[ERROR sus_compiler::codegen] Cannot codegen first_bit_idx_24 #() due to errors!
[ERROR sus_compiler::codegen] Cannot codegen permute #() due to errors!
[ERROR sus_compiler::codegen] Cannot codegen permute24 #() due to errors!
[ERROR sus_compiler::codegen] Cannot codegen disjoint_ports #() due to errors!
[ERROR sus_compiler::codegen] Cannot codegen undeteriminable_input_latency #() due to errors!
[ERROR sus_compiler::codegen] Cannot codegen conflicting_latency_declarations #() due to errors!
[ERROR sus_compiler::codegen] Cannot codegen bad_cycle #() due to errors!
[ERROR sus_compiler::codegen] Cannot codegen bad_cycle2 #() due to errors!
[ERROR sus_compiler::codegen] Cannot codegen contains_submodule_submodule #() due to errors!
[ERROR sus_compiler::codegen] Cannot codegen use_submodule_named_ports #() due to errors!
[ERROR sus_compiler::codegen] Cannot codegen contains_submodule_submodule #() due to errors!
[ERROR sus_compiler::codegen] Cannot codegen dual_port_mem #() due to errors!
[ERROR sus_compiler::codegen] Cannot codegen use_fifo #() due to errors!
[ERROR sus_compiler::codegen] Cannot codegen test_separated_domain #() due to errors!
[ERROR sus_compiler::codegen] Cannot codegen use_no_input_module #() due to errors!
[ERROR sus_compiler::codegen] Cannot codegen test_write_to_gen_var #() due to errors!
[ERROR sus_compiler::codegen] Cannot codegen use_bad_interface #() due to errors!
[ERROR sus_compiler::codegen] Cannot codegen sequenceDownFrom #() due to errors!
[ERROR sus_compiler::codegen] Cannot codegen sumUpTo #() due to errors!
[ERROR sus_compiler::codegen] Cannot codegen use_test #() due to errors!
[ERROR sus_compiler::codegen] Cannot codegen make_tree_add #() due to errors!
[ERROR sus_compiler::codegen] Cannot codegen use_replicate #() due to errors!
[ERROR sus_compiler::codegen] Cannot codegen run_instruction #() due to errors!
[ERROR sus_compiler::codegen] Cannot codegen use_no_main_interface #() due to errors!
[ERROR sus_compiler::codegen] Cannot codegen moduleWithBadDeclaration #() due to errors!
[ERROR sus_compiler::codegen] Cannot codegen moduleWithBadInterface #() due to errors!
[ERROR sus_compiler::codegen] Cannot codegen useModuleWithBadInterface #() due to errors!
[ERROR sus_compiler::codegen] Cannot codegen m #() due to errors!
[ERROR sus_compiler::codegen] Cannot codegen xyz #() due to errors!
[ERROR sus_compiler::codegen] Cannot codegen implicit_domain_forbidden #() due to errors!
[ERROR sus_compiler::codegen] Cannot codegen conflicting_domain_with_port_name #() due to errors!
[ERROR sus_compiler::codegen] Cannot codegen make_infinite_type #() due to errors!
[ERROR sus_compiler::codegen] Cannot codegen UseDualPortMem #() due to errors!
[ERROR sus_compiler::codegen] Cannot codegen example_FIFO #() due to errors!
[ERROR sus_compiler::codegen] Cannot codegen use_Iterator #() due to errors!
[ERROR sus_compiler::codegen] Cannot codegen UseBuiltinConstants #() due to errors!
[ERROR sus_compiler::codegen] Cannot codegen FailingAssert #() due to errors!
[ERROR sus_compiler::codegen] Cannot codegen latency_counting_disjoint_blocks #() due to errors!
[ERROR sus_compiler::codegen] Cannot codegen latency_counting_disjoint_blocks_merge_error #() due to errors!
[ERROR sus_compiler::codegen] Cannot codegen use_infer_me #() due to errors!
[ERROR sus_compiler::codegen] Cannot codegen inference_edge_case #() due to errors!
[ERROR sus_compiler::codegen] Cannot codegen instantiate_infer_me_with_poison_output #() due to errors!
[ERROR sus_compiler::codegen] Cannot codegen use_MultiStateLoop #() due to errors!
[ERROR sus_compiler::codegen] Cannot codegen CombineArray #() due to errors!
[ERROR sus_compiler::codegen] Cannot codegen useUnknownLatency #() due to errors!
[ERROR sus_compiler::codegen] Cannot codegen use_infer_me_conflicting_directions #() due to errors!
[ERROR sus_compiler::codegen] Cannot codegen use_infer_me_inputs_only #() due to errors!
[ERROR sus_compiler::codegen] Cannot codegen use_ranks #() due to errors!
[ERROR sus_compiler::codegen] Cannot codegen use_FIFO #() due to errors!
[ERROR sus_compiler::codegen] Cannot codegen write_to_generative_through_when #() due to errors!
[ERROR sus_compiler::codegen] Cannot codegen InstantiateTransmutes #() due to errors!
[ERROR sus_compiler::codegen] Cannot codegen StraightTransmute #() due to errors!
[ERROR sus_compiler::codegen] Cannot codegen testSlicing #() due to errors!
[ERROR sus_compiler::codegen] Cannot codegen wrong_slice_length #() due to errors!
[ERROR sus_compiler::codegen] Cannot codegen negative_slice #() due to errors!
[ERROR sus_compiler::codegen] Cannot codegen duplicate_port_names #() due to errors!
[ERROR sus_compiler::codegen] Cannot codegen make_when #() due to errors!
[ERROR sus_compiler::codegen] Cannot codegen use_make_when #() due to errors!
[ERROR sus_compiler::codegen] Cannot codegen use_module_taking_strings #() due to errors!
[ERROR sus_compiler::codegen] Cannot codegen NonGenerativeSliceBoundsMustNotICE #() due to errors!
[ERROR sus_compiler::codegen] Cannot codegen InstantiatesItself #() due to errors!
[ERROR sus_compiler::codegen] Cannot codegen TestUnknownArraySize #() due to errors!
[ERROR sus_compiler::codegen] Cannot codegen TestNextPow2 #() due to errors!
[ERROR sus_compiler::codegen] Cannot codegen GenerativeCannotHaveLatencyDeclaration #() due to errors!
[ERROR sus_compiler::codegen] Cannot codegen try_conflicting_latencies #() due to errors!
[ERROR sus_compiler::codegen] Cannot codegen AssignUnset #() due to errors!
[ERROR sus_compiler::codegen] Cannot codegen ReadUnsetArrayElem #() due to errors!
[ERROR sus_compiler::codegen] Cannot codegen RegressionForBadPort #() due to errors!
[ERROR sus_compiler::codegen] Cannot codegen WeirdlyNamedClock #() due to errors!