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Revise status and details in README.md
Updated project status and clarified tapeout details in README.
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README.md

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![](../../workflows/gds/badge.svg) ![](../../workflows/docs/badge.svg) ![](../../workflows/test/badge.svg)
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# STATUS: Working on a DIP40 version for [GF180MCU](https://www.crowdsupply.com/wafer-space/gf180mcu-run-1/). The chips from the second tapeout were delivered in summer 2025 and are currently being [tested](https://github.com/rejunity/test-z80-open-silicon/)!
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# WIP: DIP40 version for [GF180MCU](https://www.crowdsupply.com/wafer-space/gf180mcu-run-1/).
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# STATUS: The chips from the first two tapeouts were delivered in 2025, are [functional](https://github.com/rejunity/test-z80-open-silicon/) and are currently being [tested](https://github.com/hardesk/zxx-pcb)!
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Watch FOSSi Z80 made with [Tiny Tapeout](https://tinytapeout.com) waking up and sending greetings: https://github.com/rejunity/test-z80-open-silicon/
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## Tapeouts
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- [x] **FUNCTIONAL!** The **first** silicon tapeout - 130 nm **SKY130** process via [Tiny Tapeout 7](https://tinytapeout.com/runs/tt07/tt_um_rejunity_z80)
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- [x] **FUNCTIONAL!** The **first** silicon tapeout - 130 nm **SKY130** node via [Tiny Tapeout 7](https://tinytapeout.com/runs/tt07/tt_um_rejunity_z80)
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- [x] **DELIVERED/TESTING!** **All** 40 pin exposed, QFN64 package, 130 nm **SKY130** process via eFabless [CI2406 shuttle](https://github.com/rejunity/ci2406-rej-pommedeterrible-tholin)
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- [ ] Multiplexed 24 pin, 130nm **SG13g2** process via IHP experimental [2024 shuttle](https://tinytapeout.com/runs/ttihp0p2/tt_um_rejunity_z80)
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- [x] **DELIVERED!** Multiplexed 24 pin, 130nm **SG13g2** process via IHP [2025a shuttle](https://tinytapeout.com/runs/ttihp25a/tt_um_rejunity_z80)
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- [ ] **WIP!!!** 40 pin COB "Chip on Board" DIP40 PCB, 180nm **GF180MCU** process via Wafer.Space [GF180MCU Run 1](https://www.crowdsupply.com/wafer-space/gf180mcu-run-1/)
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- [ ] Multiplexed 24 pin, 130nm **SG13g2** node via IHP experimental [2024 shuttle](https://tinytapeout.com/runs/ttihp0p2/tt_um_rejunity_z80)
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- [x] **DELIVERED!** Multiplexed 24 pin, 130nm **SG13g2** node via IHP [2025a shuttle](https://tinytapeout.com/runs/ttihp25a/tt_um_rejunity_z80)
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- [ ] **WIP!!!** Classic DIP40 form factor with COB (Chip on Board), 180nm **GF180MCU** node via Wafer.Space [GF180MCU Run 1](https://www.crowdsupply.com/wafer-space/gf180mcu-run-1/)
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<p align="center" width="100%">
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<img width="610" height="802" alt="image" src="https://github.com/user-attachments/assets/f6fcc7f3-2906-4b2c-b2c7-284fb174358d" />
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- [x] Tapeout with the three different Open Source PDKs:
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- [x] SKY130 [SkyWater Technology Foundry's 130nm node](https://github.com/google/skywater-pdk)
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- [x] SG13 [IHP Foundry's BiCMOS 130nm node](https://github.com/IHP-GmbH/IHP-Open-PDK)
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- [ ] **WIP** [Global Foundry's 180nm node](https://github.com/google/gf180mcu-pdk)
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- [ ] **WIP** GF180 [Global Foundry's 180nm node](https://github.com/google/gf180mcu-pdk)
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- [x] Run [thorough tests](https://github.com/rejunity/test-z80-open-silicon) on a chip, summary:
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- [x] Z80 works in general and communicates with RP2040 / RP2350 that serves as a RAM
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- [x] **Fixed** 1 test [ZEXALL](https://mdfs.net/Software/Z80/Exerciser/) failing in general.
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- [ ] 2 tests [ZEXALL](https://mdfs.net/Software/Z80/Exerciser/) failing on undocumented flags
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- [x] Z80 functions well and communicates with RP2040 / RP2350 serving as a RAM
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- [x] **Fixed** bug in DAA instruction, caugth by [ZEXDOC/ZEXALL](https://mdfs.net/Software/Z80/Exerciser/) test suitd
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- [ ] 2 tests [ZEXALL](https://mdfs.net/Software/Z80/Exerciser/) failing on undocumented flags.
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- [x] Create a PCB adapter from QFN64 to DIP40 [https://github.com/hardesk/zxx-pcb]
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- [ ] **WIP** Produce COB (Chip-on-Board) DIP40 PCB [https://github.com/rejunity/ws0-z80-open-silicon-gf180mcu]
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- [ ] Thorough timing test of the input/output signals in compariston to original Z80

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