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kernel/mipi_rx/hi3516cv500: remove openipc_frame_ts vsync IRQ block (V4A magenta cast + VENC timeout fix) #198

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kernel/mipi_rx/hi3516cv500: remove openipc_frame_ts vsync IRQ block (V4A magenta cast + VENC timeout fix) #198

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39 changes: 0 additions & 39 deletions kernel/mipi_rx/hi3516cv500/mipi_rx_hal.c
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Original file line number Diff line number Diff line change
Expand Up @@ -2326,51 +2326,12 @@ static int mipi_rx_interrupt_route(int irq, void *dev_id)
{
volatile mipi_rx_sys_regs_t *mipi_rx_sys_regs = get_mipi_rx_sys_regs();
volatile lvds_ctrl_regs_t *lvds_ctrl_regs = NULL;
volatile mipi_ctrl_regs_t *mipi_ctrl_regs;
int i = 0;

for (i = 0; i < MIPI_RX_MAX_PHY_NUM; i++) {
mipi_rx_phy_cil_int_statis(i);
}

/*
* Frame-start dispatch (openipc_frame_ts). Runs outside the
* CHN_INT_RAW gate below because vsync IRQs alone don't set it.
* MIPI CSI-2 and LVDS vsync bits are W1C'd independently in case
* both are wired up, but openipc_frame_ts_push fires at most once
* per device per IRQ so consumers get one event per physical frame.
*/
/*
* Edge-detect on the raw vsync bits per device — see the
* matching comment in kernel/mipi_rx/mipi_rx_hal.c for the
* level-held-bit reasoning. cv500 also has the ~30–80 µs
* double-vsync quirk that the 1 ms openipc_frame_ts dedupe
* absorbs as a second line of defence.
*/
for (i = 0; i < MIPI_RX_MAX_DEV_NUM; i++) {
static bool s_vsync_was_set[MIPI_RX_MAX_DEV_NUM];
unsigned int mipi_int, lvds_int;
bool vsync_now = false;

mipi_ctrl_regs = get_mipi_ctrl_regs(i);
lvds_ctrl_regs = get_lvds_ctrl_regs(i);

mipi_int = mipi_ctrl_regs->MIPI_CTRL_INT.u32;
lvds_int = lvds_ctrl_regs->LVDS_CTRL_INT.u32;

if (mipi_int & MIPI_INT_VSYNC) {
vsync_now = true;
mipi_ctrl_regs->MIPI_CTRL_INT_RAW.u32 = MIPI_INT_VSYNC;
}
if (lvds_int & LVDS_INT_VSYNC) {
vsync_now = true;
lvds_ctrl_regs->LVDS_CTRL_INT_RAW.u32 = LVDS_INT_VSYNC;
}
if (vsync_now && !s_vsync_was_set[i])
openipc_frame_ts_push(i, OPENIPC_FT_EVT_MIPI_FS);
s_vsync_was_set[i] = vsync_now;
}

for (i = 0; i < MIPI_RX_MAX_DEV_NUM; i++) {
lvds_ctrl_regs = get_lvds_ctrl_regs(i);
if (lvds_ctrl_regs->CHN_INT_RAW.u32) {
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8 changes: 2 additions & 6 deletions kernel/mipi_rx/hi3516cv500/mipi_rx_hal.h
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Original file line number Diff line number Diff line change
Expand Up @@ -15,12 +15,8 @@
#define MIPI_RX_MIN_EXT_DATA_TYPE_BIT_WIDTH 8

#define MIPI_CIL_INT_MASK 0x00003f3f
/* Vsync bits unmasked so frame-start propagates to mipi_rx_interrupt_route,
* where openipc_frame_ts dispatches it. Error-stat bits unchanged. */
#define MIPI_INT_VSYNC (1u << 4) /* MIPI_CTRL_INT.int_vsync */
#define LVDS_INT_VSYNC (1u << 28) /* LVDS_CTRL_INT.lvds_vsync */
#define MIPI_CTRL_INT_MASK 0x00030013
#define LVDS_CTRL_INT_MASK 0x1f110000
#define MIPI_CTRL_INT_MASK 0x00030003
#define LVDS_CTRL_INT_MASK 0x0f110000 /* lvds_vsync_msk and lane0~3_sync_err_msk ignore, not err int */
#define MIPI_FRAME_INT_MASK 0x000f0000
#define MIPI_PKT_INT1_MASK 0x0001000f
#define MIPI_PKT_INT2_MASK 0x000f000f
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