Add test scenario for tbit error in RxLenH

verification/cocotb/top/lib_i3c_top/i3c_recovery_interface_fixed.py

@@ -307,7 +307,7 @@ async def command_write_abort(self, address, command, data=None, abort_after_byt
         await self.controller.send_stop()
         self.controller.give_bus_control()
 
-    async def command_write_tbit_error(self, address, command, data=None, error_byte_index=0):
+    async def command_write_tbit_error(self, address, command, data=None, error_byte_index=0, end_with_rstart=False):
         """
         Issues a write command with an intentional T-bit (parity) error on a specific byte.
 
@@ -342,7 +342,10 @@ async def command_write_tbit_error(self, address, command, data=None, error_byte
                 inject_error = (i == error_byte_index)
                 await self.controller.send_byte_tbit(byte, inject_tbit_err=inject_error)
 
-        await self.controller.send_stop()
+        if not end_with_rstart:
+            await self.controller.send_stop()
+        else:
+            await self.controller.send_start()
         self.controller.give_bus_control()
 
     async def command_read_tbit_error(self, address, command, error_byte_index=0):

verification/cocotb/top/lib_i3c_top/test_recovery.py

@@ -1208,6 +1208,63 @@ async def rapid_fire_scenario():
             )
     await run_scenario("Scenario 15: Rapid-fire aborts (5x)", rapid_fire_scenario)
 
+    # =========================================================================
+    # Scenario 16: T-bit (parity) error on Length MSB byte (detection disabled)
+    # Scenario 17: T-bit (parity) error on Length MSB byte (detection enabled)
+    # =========================================================================
+    async def lenh_pec_err_scenario(pec_det_en=True):
+        # Set PEC detection (bit 7)
+        err_ctrl = dword2int(
+            await tb.read_csr(tb.reg_map.I3C_EC.TTI.TARGET_ERR_CTRL.base_addr, 4)
+        )
+        pec_det_en_value = (err_ctrl | (1 << 7)) if pec_det_en else (err_ctrl & ~(1 << 7))
+
+        await tb.write_csr(
+            tb.reg_map.I3C_EC.TTI.TARGET_ERR_CTRL.base_addr,
+            int2dword(pec_det_en_value), 4
+        )
+
+        tb.te_error_monitor.expect_error(2)
+        await recovery.command_write_tbit_error(
+            VIRT_DYNAMIC_ADDR,
+            I3cRecoveryInterface.Command.RECOVERY_CTRL,
+            [0xAA, 0xBB, 0xCC],
+            2,  # Length MSB byte
+            end_with_rstart=True
+        )
+        tb.te_error_monitor.clear_expectations()
+
+        # Bring back previous PEC detection
+        await tb.write_csr(
+            tb.reg_map.I3C_EC.TTI.TARGET_ERR_CTRL.base_addr,
+            int2dword(err_ctrl), 4
+        )
+
+        status = dword2int(
+            await tb.read_csr(
+                tb.reg_map.I3C_EC.SECFWRECOVERYIF.DEVICE_STATUS_0.base_addr, 4
+            )
+        )
+        protocol_status = (status >> 8) & 0xFF
+
+        # Ensure CRC error (0x4) is reported if detection enabled
+        if pec_det_en:
+            assert protocol_status == 0x4
+        else:
+            assert protocol_status == 0x0
+
+    await run_scenario(
+        "Scenario 16: T-bit error on Length MSB (error detection disabled)",
+        lenh_pec_err_scenario,
+        False
+    )
+
+    await run_scenario(
+        "Scenario 17: T-bit error on Length MSB (error detection enabled)",
+        lenh_pec_err_scenario,
+        True
+    )
+
     # =========================================================================
     # Final Verification: Do a complete valid write and read cycle
     # =========================================================================