·
96 commits
to refs/heads/main
since this release
👀 What's Changed
This release features powerful extensions for the gold physical design engine, further enhancing its capabilities for layout generation. Among these is an all-new maximum-effort mode that explores even more corners of the solution space. Additional flags enforce straight inverter gates or additional spacing for primary input pins. Furthermore, fiction gained a crossing minimization engine adapted from GraphViz. Stay tuned for crossing-free physical design flows!
As per usual, we fixed bugs, improved performance, and updated dependencies. Also, you can find new references to our latest publications in the documentation.
Full CHANGELOG: v0.6.11...v0.6.12
Many thanks to all contributors!
✨ Features and Enhancements
- ✨ Added a Reimplementation of GraphViz's "Mincross" Algorithm for Edge Crossing Minimization in Networks @hibenj (#736)
- ✨ Extended the
areacommand to also report layout width and height in nanometers @marcelwa (#828) - ✨ Skip tiles for PI placement in
gold@simon1hofmann (#820) - ✨ Added flag to
goldto enforce NOT gates to be routed non-bending only @simon1hofmann (#784) - ✨ Maximum-effort mode for
gold@simon1hofmann (#743) - 🎨 Small changes in
is_operationaland addedPRUNING_BASEDoption to gate design @Drewniok (#760) - ⚗️ Added further experiments for
QuickCell@Drewniok (#762) - ⚗️ Updated experiment due to previous changes in the code base @Drewniok (#769)
- ⚗️ Added missing experiment script for the minimal gate design @Drewniok (#763)
- ⚗️ Added missing figure of merit experiment @Drewniok (#778)
⚡️ Performance
- ⚡️ Speed up
hexagonalization@simon1hofmann (#837)
🐛 Bug Fixes
- 🐛 Fix the
clang-tidyCI's attempt to push thread comments from fork runs @marcelwa (#853) - 🐛 Added error handling in experiment for disabled
ALGLIBlibrary @Drewniok (#826) - 🔧 Adjust compilation database in order to fix
clang-tidybehavior @marcelwa (#840) - 👷 Fallback to default values for some options in clang-tidy CI configuration @marcelwa (#829)
- 🚨 Fixed
clang-tidywarnings @simon1hofmann (#827) - 🐛 Fixed PO extension in
hexagonalization@simon1hofmann (#819) - 🐛 Fixed PO location in
post_layout_optimization@simon1hofmann (#796) - 👷 Adjust fetch depth in clang-tidy CI to ensure complete history is available @marcelwa (#793)
- 👷 Adjust the Clang-Tidy Workflow to Run on Pull Request Target Triggers Exclusively @marcelwa (#792)
- 👷 Update clang-tidy CI to use the
pull_request_targettrigger @marcelwa (#791) - 👷 Add permissions to the
clang-tidyCI @marcelwa (#790) - 🐛 Fixed band bending resilience calculation for unspecified
transition_type@Drewniok (#770) - 🐛 Fixed I/O cell handling in
assign_cell_type@Drewniok (#747) - 🐛 Fixes to SiDB Simulation Core Code @wlambooy (#738)
- 🐛 Add missing
clonemember function to pyfiction's SiDB lattices @marcelwa (#748)
📝 Documentation
- 📝 Update TCAD journal paper @simon1hofmann (#839)
- 📝 Added recent publications (IEEE-NANO, TCAD, ASP-DAC 2026) @Drewniok (#817)
- 📝 Added DATE 2025 reference @Drewniok (#753)
- 📝 Added ISCAS 2025 reference @Drewniok (#776)
✅ Testing
👷 CI
- 👷 Switch to the
Ninjagenerator for Windows CI runs to make use ofccache@marcelwa (#865) - 👷 Updated the code coverage config @marcelwa (#562)
- 🔥 Dropped Python 3.9 support @marcelwa (#864)
- 🐛 Fix the
clang-tidyCI's attempt to push thread comments from fork runs @marcelwa (#853) - 👷 Fallback to default values for some options in clang-tidy CI configuration @marcelwa (#829)
- 👷 Adjust fetch depth in clang-tidy CI to ensure complete history is available @marcelwa (#793)
- 👷 Adjust the Clang-Tidy Workflow to Run on Pull Request Target Triggers Exclusively @marcelwa (#792)
- 👷 Update clang-tidy CI to use the
pull_request_targettrigger @marcelwa (#791) - 👷 Add permissions to the
clang-tidyCI @marcelwa (#790) - 👷 Modernize and simplify the clang-tidy CI @marcelwa (#785)
- 🔥 Drop Windows 2019 and v142 support @marcelwa (#757)
⬆️ Dependencies
81 changes
- ⬆️👨💻 Update Submodules @renovate[bot] (#867)
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