constrained-random

RV32IM RISC-V CPU core with a full UVM verification environment and ISA-compliance via Spike (DPI-C): constrained-random, SVA, coverage, Python debug tools, and CI.

python jenkins cpu processor verification dpi spike riscv isa vcs systemverilog uvm constrained-random sva rv32im questa functional-coverage

Updated Aug 20, 2025
SystemVerilog

abdo-ehab-euv / sram-controller-uvm-verification

Star

SystemVerilog and UVM verification of an 8x8 SRAM memory controller with coverage, scoreboard, regression scripts, and bug-demo dashboard.

python tcl verification rtl scoreboard sram regression-testing systemverilog modelsim uvm testbench constrained-random memory-controller questa hardware-verification functional-coverage uvm-verification directed-testing design-verification-project

Updated May 14, 2026
SystemVerilog

Tharunreddym / riscv-pipeline-verification

Star

UVM-based verification environment for a 5-stage RV32I RISC-V pipeline using constrained-random testing, DPI-C golden reference modeling, assertions, scoreboarding, functional coverage, and 20-seed QuestaSim regression debugging.

c-plus-plus verification verilog scoreboard regression-testing systemverilog uvm constrained-random risc-v asic-verification questa dpi-c functional-coverage rtl-verification pipeline-verification

Updated May 19, 2026
SystemVerilog

Hampton-bit / uvm-yapp-router-verification-yapp-uvc

Star

UVM testbench for verifying a packet router using the YAPP (Yet Another Packet Protocol)

router uvm constrained-random functional-verification asic-verification hardware-verification yapp

Updated Jun 24, 2025
SystemVerilog

Tharunreddym / axi4-verification

Star

AXI4 Memory Controller UVM Verification Environment with real Siemens Questa seed-1 simulation logs, scoreboard checks, functional coverage summaries, and documented burst-read debug fix.

python scoreboard regression-testing systemverilog uvm constrained-random semiconductor digital-design sva questa axi4 functional-coverage rtl-verification eda-playground

Updated May 19, 2026
SystemVerilog

AryaD-ece / systemverilog-valid-ready-pipeline

Star

Backpressure-safe 1-stage valid-ready pipeline in SystemVerilog with constrained-random verification, assertions (SVA), and waveform validation.

fpga pipeline verification systemverilog constrained-random digital-design rtl-design hardware-design valid-ready

Updated Apr 28, 2026
SystemVerilog

Nam24-dot / apb4-axi4-uvm-verification-portfolio

Star

Public portfolio of APB4 and AXI4 verification methodology using SystemVerilog, UVM, SVA and coverage.

coverage systemverilog uvm constrained-random sva axi4 design-verification rtl-verification apb4

Updated Jun 2, 2026

Tharunreddym / sram-uvm-verification

Star

SRAM subsystem verification using SystemVerilog UVM, SVA assertions, scoreboard, functional coverage, and 20-seed QuestaSim regression evidence from EDA Playground.

assertions scoreboard sram regression-testing systemverilog uvm constrained-random digital-design questa functional-coverage eda-playground verification-environment

Updated May 19, 2026
SystemVerilog

k-pitaliya / FSM-Digital-Controller

Star

Multi-state Mealy/Moore FSM in SystemVerilog with SVA assertions, constrained-random testbenches, and functional coverage — synthesizable on Xilinx FPGAs

fsm fpga verification xilinx systemverilog constrained-random digital-design sva mealy moore rtl-design functional-coverage

Updated Apr 12, 2026
SystemVerilog

alwilson / smt2_rand_sampler

Star

Explorations in Uniform Sampling of SMT2 Constraints

constraints smt2 constrained-random

Updated Oct 5, 2023
Python

Mohank-VLSI-Verification / sv-verification-portfolio

Star

UVM-based verification portfolio for APB, AXI, I2C, SPI, and UART protocols. Class-based testbenches with sequence library, reference model, dual TLM-FIFO scoreboard, functional coverage (uvm_subscriber), SVA assertions, and Makefile/TCL build flow.

i2c spi tlm uart constrained-random xilinx-vivado axi amba apb asic-verification design-verification functional-coverage uvm-verification assertion-based-verification reference-model coverage-driven-verification

Updated Jun 17, 2026
SystemVerilog

Samarth1712 / axi4_mem_verification

Star

AXI4 SRAM controller verification environment using SystemVerilog, UVM-lite, SVA, constrained-random testing, and functional coverage.

coverage verification rtl systemverilog uvm constrained-random sva functional-verification memory-controller axi4 protocol-verification

Updated May 31, 2026
SystemVerilog

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constrained-random

Here are 16 public repositories matching this topic...

OSVVM / OSVVM

fvutils / pyvsc

agra-uni-bremen / crave

imaginationtech / constrainedrandom

gopro-uvm-rtl-verification / RISC-V-CPU-Core-UVM-Based-ISA-Compliance-Verification

abdo-ehab-euv / sram-controller-uvm-verification

Tharunreddym / riscv-pipeline-verification

Hampton-bit / uvm-yapp-router-verification-yapp-uvc

Tharunreddym / axi4-verification

AryaD-ece / systemverilog-valid-ready-pipeline

Nam24-dot / apb4-axi4-uvm-verification-portfolio

Tharunreddym / sram-uvm-verification

k-pitaliya / FSM-Digital-Controller

alwilson / smt2_rand_sampler

Mohank-VLSI-Verification / sv-verification-portfolio

Samarth1712 / axi4_mem_verification

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