This repository contains source code for past labs and projects involving FPGA and Verilog based designs

Binary adder implementation in the Game of Life written in JavaScript using canvas.

Various electronic systems including ADC/DAC, filters, and simulations using NI Multisim.

A Java binary calculator based on a system of gates

A 4bit Multiplier in VHDL

Digital System Design Lab Codes using Verilog

A simulation where I can connect virtual logic gates and build virtual CIs.

This repository contains Verilog HDL implementations of Half Adders, Full Adders, and 4-bit Adders, designed at three different abstraction levels: Gate Level, Dataflow Level, and Behavioral Level. These designs are fundamental to digital electronics, and this project showcases the versatility of Verilog in modeling and simulating digital circuits.

Download my Redstone World: https://www.planetminecraft.com/project/redstone-circuits-6024948/

Combinational circuits in Verilog - Adders, Subtractor, MUX, Decoder, Encoder, Comparator and 16-bit ALU. Step 2 of 8 in a VLSI portfolio roadmap building to a 16-bit pipelined RISC processor.

VHDL implementations of half-adders, full-adders, and a 4-bit adder for digital circuit design

All the various adders in Verilog!

Different adders code in VHDL and Comparison

Labwork on Logic Design implementation in Verilog on a Basys3 FPGA Module

This repository contains HWs and material from the nand to tetris course

Digital Circuits: Half Adder.

A repository for some modules I made while learning Verilog

A Java program that converts a binary number into it's two's complement equivalent. This is used within the SimpleBinaryCalculator repository.

Digital Design laboratory project demonstrating binary arithmetic circuits, including Half Adder, Full Adder, Half Subtractor, Full Subtractor, with interactive NI Multisim simulations, truth tables, and logical equation analysis (Logic Design, UNIWA).

A configurable full adder IP with three implementation approaches (simple XOR/AND, modular half adder, carry lookahead) following Vyges conventions. Includes comprehensive verification with SystemVerilog, UVM, and Cocotb testbenches supporting multiple simulators (Icarus, Verilator, Questa, VCS, Xcelium). Production-ready for ASIC/FPGA w/ 500MHz