This repository provides the source code for RISE framework. RISE can be used as a generic framework Real-Time Intelligent Video Surveillance on FPGA.

HW/SW co-simulation of a radar collision monitor on Zynq-7000. MATLAB stimulus → VHDL RTL → AXI4-Lite SoC → SystemVerilog testbench with Zynq VIP. Fully simulation-verified.

Integração de HPS para FPGA por meio de Biblioteca Assembly na Cyclone V

INT8 Systolic-Array AI Accelerator on Zynq SoC with HW-SW Co-Design and Roofline Performance Analysis

Image super-resolution carved into silicon (FPGA Ignite 2024)

🎥 Explore how video generators can reveal implicit world rules with RISE-Video, enhancing understanding in computer vision research.

HW-SW Co-Design framework for custom NPU: Parameterized systolic array RTL verification via cocotb and multi-objective design space exploration (DSE) with analytical performance modeling.

Hardware-software co-design for BitNet inference on multicore RISC-V using CVA6, Ara (RVV), and a ternary-optimized Gemmini.

Hardware/software co-design of pipelined AES-128 using Zynq SoC for IIoT gateways