- What Vyges IP Catalog is
- How IPs are curated
- Licensing philosophy
- How metadata works
- How updates are handled
Vyges IP Catalog
- 4 followers
- United States of America
- https://vyges.com/products/vycatalog
Popular repositories Loading
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sky130-sar-adc
sky130-sar-adc PublicSilicon-proven 12-bit fully-differential SAR-ADC in SKY130
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sky130-delta-sigma-adc
sky130-delta-sigma-adc Public12-bit 10-KSPS incremental delta-sigma ADC in SKY130
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opentitan-uart
opentitan-uart PublicOpenTitan UART IP - Full duplex serial communication peripheral with programmable baud rate, RX/TX buffers, and interrupt support
SystemVerilog
Repositories
- vyges-ip-catalog Public
Auto-synced cache of every vyges-metadata.json from the vyges-ip org. Single source of truth for downstream tooling.
vyges-ip/vyges-ip-catalog’s past year of commit activity - opentitan-uart Public
OpenTitan UART IP - Full duplex serial communication peripheral with programmable baud rate, RX/TX buffers, and interrupt support
vyges-ip/opentitan-uart’s past year of commit activity - fast-fourier-transform-ip Public
Configurable, high-performance FFT hardware IP core for ASIC/FPGA. Pipelined radix-2 DIF, 256–4096-point support, 16-bit fixed-point, double-buffered memory,...
vyges-ip/fast-fourier-transform-ip’s past year of commit activity - .github Public
vyges-ip/.github’s past year of commit activity - tlul-apb-adapter Public
Generic TL-UL to APB protocol adapter. Connects any APB peripheral to a TileLink Uncached Lightweight (TL-UL) crossbar for Ibex/OpenTitan RISC-V SoCs.
vyges-ip/tlul-apb-adapter’s past year of commit activity - vyges-rv-dbg-tlul Public
RISC-V Debug Module with TL-UL bus — Vyges-authored wrapper over pulp-riscv-dbg. Provides TL-UL slave (regs + mem) + TL-UL master (sba) + JTAG TAP for direct integration into Vyges TL-UL SoCs without OpenTitan lifecycle/alert infrastructure.
vyges-ip/vyges-rv-dbg-tlul’s past year of commit activity - opentitan-tlul Public
TL-UL is a lightweight (uncached) bus that combines the point-to-point split-transaction features of the powerful TileLink (or AMBA AXI) 5-channel bus without the high pin-count overhead.
vyges-ip/opentitan-tlul’s past year of commit activity
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