System Reset Controller (sysrst_ctrl) that provides programmable hardware-level responses to trusted IOs and basic board-level reset sequencing capabilities

The mailbox IP block in the OpenTitan Integrated design implements a request-response channel that the host System-on-Chip (SoC) may use to request security ser

Entropy Distribution Network (EDN) interfaces to the CSRNG IP module

Cryptographically Secure Random Number Generator (CSRNG)

This document specifies the OTP MACRO hardware IP functionality.

OpenTitan UART IP - Full duplex serial communication peripheral with programmable baud rate, RX/TX buffers, and interrupt support

Keccak Message Authentication Code (KMAC) and Secure Hashing Algorithm 3 (SHA3)

OpenTitan Flash Ctrl IP block

ROM controller (rom_ctrl) is the connection between the chip and its ROM

OpenTitan Prim Xilinx Ultrascale IP block

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Analog to Digital Converter Control Interface

OpenTitan Rv Core Ibex IP block

OpenTitan Prim Generic IP block

I2C controller

RISC-V Debug System wrapper functionality

Entropy Source: interface to an external physical random noise generator

SRAM memory controller

Generic TL-UL to APB protocol adapter. Connects any APB peripheral to a TileLink Uncached Lightweight (TL-UL) crossbar for Ibex/OpenTitan RISC-V SoCs.

The Direct Memory Access (DMA) controller is a peripheral within the OpenTitan system-on-chip (SoC).